test/CodeGen/MIR/Mips/setRegClassOrRegBank.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600

# Check there are no COPY instructions surrounding ADDVI_W instruction.
# MIParser sets RegClassOrRegBank for parsed virtual registers.
# Constraining register classes when G_INTRINSIC intrinsic(@llvm.mips.addvi.w)
# gets selected into ADDVI_W works as expected.
# Check that setRegClassOrRegBank.ll has same output.

--- |

  declare <4 x i32> @llvm.mips.addvi.w(<4 x i32>, i32 immarg)
  define void @add_v4i32_builtin_imm(<4 x i32>* %a, <4 x i32>* %c) { entry: ret void }

...
---
name:            add_v4i32_builtin_imm
alignment:       4
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $a0, $a1

    ; P5600-LABEL: name: add_v4i32_builtin_imm
    ; P5600: liveins: $a0, $a1
    ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
    ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
    ; P5600: [[LOAD:%[0-9]+]]:msa128w(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
    ; P5600: [[ADDVI_W:%[0-9]+]]:msa128w(<4 x s32>) = ADDVI_W [[LOAD]](<4 x s32>), 25
    ; P5600: G_STORE [[ADDVI_W]](<4 x s32>), [[COPY1]](p0) :: (store 16 into %ir.c)
    ; P5600: RetRA
    %0:_(p0) = COPY $a0
    %1:_(p0) = COPY $a1
    %2:_(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
    %3:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.mips.addvi.w), %2(<4 x s32>), 25
    G_STORE %3(<4 x s32>), %1(p0) :: (store 16 into %ir.c)
    RetRA

...