commit e6fb6db5680e297e0b99739dcfbdb4d72ddd752b
author Petar Avramovic <Petar.Avramovic@rt-rk.com> Tue Oct 22 14:25:37 2019 +0000
committer Petar Avramovic <Petar.Avramovic@rt-rk.com> Tue Oct 22 14:25:37 2019 +0000
tree 21969fd96012bfba3cfbd70379a9f615d38185ca
parent ee57dd49214a7ca74f0b01111bf0ce16d42cecb5

[MIParser] Set RegClassOrRegBank during instruction parsing

MachineRegisterInfo::createGenericVirtualRegister sets
RegClassOrRegBank to static_cast<RegisterBank *>(nullptr).
MIParser on the other hand doesn't. When we attempt to constrain
Register Class on such VReg, additional COPY is generated.
This way we avoid COPY instructions showing in test that have MIR
input while they are not present with llvm-ir input that was used
to create given MIR for a -run-pass test.

Differential Revision: https://reviews.llvm.org/D68946


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375502 91177308-0d34-0410-b5e6-96231b3b80d8