tree dda3c3e21a33a87a3d10740f2d456950265cb6cb
parent e18b4e0759b3384149b4680c8c4d301205fc170d
author Alex Bradbury <asb@lowrisc.org> 1547719479 +0000
committer Alex Bradbury <asb@lowrisc.org> 1547719479 +0000

[RISCV] Add codegen support for RV64A

In order to support codegen RV64A, this patch:
* Introduces masked atomics intrinsics for atomicrmw operations and cmpxchg
  that use the i64 type. These are ultimately lowered to masked operations
  using lr.w/sc.w, but we need to use these alternate intrinsics for RV64
  because i32 is not legal
* Modifies RISCVExpandPseudoInsts.cpp to handle PseudoAtomicLoadNand64 and
  PseudoCmpXchg64
* Modifies the AtomicExpandPass hooks in RISCVTargetLowering to sext/trunc as
  needed for RV64 and to select the i64 intrinsic IDs when necessary
* Adds appropriate patterns to RISCVInstrInfoA.td
* Updates test/CodeGen/RISCV/atomic-*.ll to show RV64A support

This ends up being a fairly mechanical change, as the logic for RV32A is
effectively reused.

Differential Revision: https://reviews.llvm.org/D53233


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351422 91177308-0d34-0410-b5e6-96231b3b80d8