| //===-- RISCVInstrInfo.cpp - RISCV Instruction Information ------*- C++ -*-===// |
| // |
| // The LLVM Compiler Infrastructure |
| // |
| // This file is distributed under the University of Illinois Open Source |
| // License. See LICENSE.TXT for details. |
| // |
| //===----------------------------------------------------------------------===// |
| // |
| // This file contains the RISCV implementation of the TargetInstrInfo class. |
| // |
| //===----------------------------------------------------------------------===// |
| |
| #include "RISCVInstrInfo.h" |
| #include "RISCV.h" |
| #include "RISCVSubtarget.h" |
| #include "RISCVTargetMachine.h" |
| #include "llvm/ADT/STLExtras.h" |
| #include "llvm/ADT/SmallVector.h" |
| #include "llvm/CodeGen/MachineFunctionPass.h" |
| #include "llvm/CodeGen/MachineInstrBuilder.h" |
| #include "llvm/CodeGen/MachineRegisterInfo.h" |
| #include "llvm/Support/ErrorHandling.h" |
| #include "llvm/Support/TargetRegistry.h" |
| |
| #define GET_INSTRINFO_CTOR_DTOR |
| #include "RISCVGenInstrInfo.inc" |
| |
| using namespace llvm; |
| |
| RISCVInstrInfo::RISCVInstrInfo() |
| : RISCVGenInstrInfo(RISCV::ADJCALLSTACKDOWN, RISCV::ADJCALLSTACKUP) {} |
| |
| void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB, |
| MachineBasicBlock::iterator MBBI, |
| const DebugLoc &DL, unsigned DstReg, |
| unsigned SrcReg, bool KillSrc) const { |
| assert(RISCV::GPRRegClass.contains(DstReg, SrcReg) && |
| "Impossible reg-to-reg copy"); |
| |
| BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), DstReg) |
| .addReg(SrcReg, getKillRegState(KillSrc)) |
| .addImm(0); |
| } |
| |
| void RISCVInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, |
| MachineBasicBlock::iterator I, |
| unsigned SrcReg, bool IsKill, int FI, |
| const TargetRegisterClass *RC, |
| const TargetRegisterInfo *TRI) const { |
| DebugLoc DL; |
| if (I != MBB.end()) |
| DL = I->getDebugLoc(); |
| |
| if (RC == &RISCV::GPRRegClass) |
| BuildMI(MBB, I, DL, get(RISCV::SW)) |
| .addReg(SrcReg, getKillRegState(IsKill)) |
| .addFrameIndex(FI) |
| .addImm(0); |
| else |
| llvm_unreachable("Can't store this register to stack slot"); |
| } |
| |
| void RISCVInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, |
| MachineBasicBlock::iterator I, |
| unsigned DstReg, int FI, |
| const TargetRegisterClass *RC, |
| const TargetRegisterInfo *TRI) const { |
| DebugLoc DL; |
| if (I != MBB.end()) |
| DL = I->getDebugLoc(); |
| |
| if (RC == &RISCV::GPRRegClass) |
| BuildMI(MBB, I, DL, get(RISCV::LW), DstReg).addFrameIndex(FI).addImm(0); |
| else |
| llvm_unreachable("Can't load this register from stack slot"); |
| } |