diff --git a/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index 419e711..da5c42d 100644
--- a/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -25,6 +25,16 @@
 using namespace LegalizeMutations;
 using namespace LegalityPredicates;
 
+
+static LegalityPredicate isMultiple32(unsigned TypeIdx,
+                                      unsigned MaxSize = 512) {
+  return [=](const LegalityQuery &Query) {
+    const LLT Ty = Query.Types[TypeIdx];
+    const LLT EltTy = Ty.getScalarType();
+    return Ty.getSizeInBits() <= MaxSize && EltTy.getSizeInBits() % 32 == 0;
+  };
+}
+
 AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST,
                                          const GCNTargetMachine &TM) {
   using namespace TargetOpcode;
@@ -121,15 +131,12 @@
   getActionDefinitionsBuilder(G_FCONSTANT)
     .legalFor({S32, S64, S16});
 
-  // G_IMPLICIT_DEF is a no-op so we can make it legal for any value type that
-  // can fit in a register.
-  // FIXME: We need to legalize several more operations before we can add
-  // a test case for size > 512.
   getActionDefinitionsBuilder(G_IMPLICIT_DEF)
-    .legalIf([=](const LegalityQuery &Query) {
-        return Query.Types[0].getSizeInBits() <= 512;
-    })
-    .clampScalar(0, S1, S512);
+    .legalFor({S1, S32, S64, V2S32, V4S32, V2S16, V4S16, GlobalPtr,
+               ConstantPtr, LocalPtr, FlatPtr, PrivatePtr})
+    .legalFor({LLT::vector(3, 16)})// FIXME: Hack
+    .clampScalarOrElt(0, S32, S512)
+    .legalIf(isMultiple32(0));
 
 
   // FIXME: i1 operands to intrinsics should always be legal, but other i1
diff --git a/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir b/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
index 10671b4..cc8471a 100644
--- a/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
+++ b/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
@@ -187,11 +187,19 @@
   bb.0:
 
     ; CHECK-LABEL: name: extract_vector_elt_0_v2i8_i32
+    ; CHECK: [[DEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
     ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
-    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32)
+    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY [[DEF]](<2 x s32>)
+    ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
+    ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[UV]], [[C1]](s32)
+    ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[UV1]], [[C1]](s32)
+    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
+    ; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C1]](s32)
+    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ASHR]](s32), [[ASHR1]](s32)
     ; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<2 x s32>), [[C]](s32)
-    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[EVEC]](s32)
-    ; CHECK: $vgpr0 = COPY [[COPY]](s32)
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[EVEC]](s32)
+    ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
     %0:_(<2 x s8>) = G_IMPLICIT_DEF
     %1:_(s32) = G_CONSTANT i32 0
     %2:_(s8) = G_EXTRACT_VECTOR_ELT %0, %1
@@ -225,11 +233,19 @@
   bb.0:
 
     ; CHECK-LABEL: name: extract_vector_elt_0_v2i1_i32
+    ; CHECK: [[DEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
     ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
-    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32)
+    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
+    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY [[DEF]](<2 x s32>)
+    ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
+    ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[UV]], [[C1]](s32)
+    ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[UV1]], [[C1]](s32)
+    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
+    ; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C1]](s32)
+    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ASHR]](s32), [[ASHR1]](s32)
     ; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<2 x s32>), [[C]](s32)
-    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[EVEC]](s32)
-    ; CHECK: $vgpr0 = COPY [[COPY]](s32)
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[EVEC]](s32)
+    ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
     %0:_(<2 x s1>) = G_IMPLICIT_DEF
     %1:_(s32) = G_CONSTANT i32 0
     %2:_(s1) = G_EXTRACT_VECTOR_ELT %0, %1
@@ -244,13 +260,20 @@
   bb.0:
 
     ; CHECK-LABEL: name: extract_vector_elt_0_v2i1_i1
+    ; CHECK: [[DEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
     ; CHECK: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
-    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
-    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C1]](s32)
+    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
+    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY [[DEF]](<2 x s32>)
+    ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
+    ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[UV]], [[C1]](s32)
+    ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[UV1]], [[C1]](s32)
+    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
+    ; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C1]](s32)
+    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ASHR]](s32), [[ASHR1]](s32)
     ; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[C]](s1)
     ; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<2 x s32>), [[SEXT]](s32)
-    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[EVEC]](s32)
-    ; CHECK: $vgpr0 = COPY [[COPY]](s32)
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[EVEC]](s32)
+    ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
     %0:_(<2 x s1>) = G_IMPLICIT_DEF
     %1:_(s1) = G_CONSTANT i1 false
     %2:_(s1) = G_EXTRACT_VECTOR_ELT %0, %1
diff --git a/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir b/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir
index 75bbcaa..a8bb0a0 100644
--- a/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir
+++ b/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir
@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck %s
 
 ---
 name: test_extract_lo32_i64
@@ -111,10 +111,13 @@
 body: |
   bb.0:
     ; CHECK-LABEL: name: extract_s8_v4s8_offset0
-    ; CHECK: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
-    ; CHECK: [[EXTRACT:%[0-9]+]]:_(s16) = G_EXTRACT [[DEF]](<4 x s16>), 0
-    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[EXTRACT]](s16)
-    ; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)
+    ; CHECK: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[DEF]](<4 x s32>)
+    ; CHECK: [[ANYEXT:%[0-9]+]]:_(<4 x s16>) = G_ANYEXT [[TRUNC]](<4 x s8>)
+    ; CHECK: [[EXTRACT:%[0-9]+]]:_(s16) = G_EXTRACT [[ANYEXT]](<4 x s16>), 0
+    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[EXTRACT]](s16)
+    ; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s8)
+    ; CHECK: $vgpr0 = COPY [[ANYEXT1]](s32)
     %0:_(<4 x s8>) = G_IMPLICIT_DEF
     %1:_(s8) = G_EXTRACT %0, 0
     %2:_(s32) = G_ANYEXT %1
@@ -128,10 +131,13 @@
 body: |
   bb.0:
     ; CHECK-LABEL: name: extract_s8_v4s8_offset8
-    ; CHECK: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
-    ; CHECK: [[EXTRACT:%[0-9]+]]:_(s16) = G_EXTRACT [[DEF]](<4 x s16>), 16
-    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[EXTRACT]](s16)
-    ; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)
+    ; CHECK: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[DEF]](<4 x s32>)
+    ; CHECK: [[ANYEXT:%[0-9]+]]:_(<4 x s16>) = G_ANYEXT [[TRUNC]](<4 x s8>)
+    ; CHECK: [[EXTRACT:%[0-9]+]]:_(s16) = G_EXTRACT [[ANYEXT]](<4 x s16>), 16
+    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[EXTRACT]](s16)
+    ; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s8)
+    ; CHECK: $vgpr0 = COPY [[ANYEXT1]](s32)
     %0:_(<4 x s8>) = G_IMPLICIT_DEF
     %1:_(s8) = G_EXTRACT %0, 8
     %2:_(s32) = G_ANYEXT %1
@@ -145,10 +151,13 @@
 body: |
   bb.0:
     ; CHECK-LABEL: name: extract_s8_v4s8_offset16
-    ; CHECK: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
-    ; CHECK: [[EXTRACT:%[0-9]+]]:_(s16) = G_EXTRACT [[DEF]](<4 x s16>), 32
-    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[EXTRACT]](s16)
-    ; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)
+    ; CHECK: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[DEF]](<4 x s32>)
+    ; CHECK: [[ANYEXT:%[0-9]+]]:_(<4 x s16>) = G_ANYEXT [[TRUNC]](<4 x s8>)
+    ; CHECK: [[EXTRACT:%[0-9]+]]:_(s16) = G_EXTRACT [[ANYEXT]](<4 x s16>), 32
+    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[EXTRACT]](s16)
+    ; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s8)
+    ; CHECK: $vgpr0 = COPY [[ANYEXT1]](s32)
     %0:_(<4 x s8>) = G_IMPLICIT_DEF
     %1:_(s8) = G_EXTRACT %0, 16
     %2:_(s32) = G_ANYEXT %1
@@ -162,10 +171,13 @@
 body: |
   bb.0:
     ; CHECK-LABEL: name: extract_s8_v4s8_offset24
-    ; CHECK: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
-    ; CHECK: [[EXTRACT:%[0-9]+]]:_(s16) = G_EXTRACT [[DEF]](<4 x s16>), 48
-    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[EXTRACT]](s16)
-    ; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)
+    ; CHECK: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[DEF]](<4 x s32>)
+    ; CHECK: [[ANYEXT:%[0-9]+]]:_(<4 x s16>) = G_ANYEXT [[TRUNC]](<4 x s8>)
+    ; CHECK: [[EXTRACT:%[0-9]+]]:_(s16) = G_EXTRACT [[ANYEXT]](<4 x s16>), 48
+    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[EXTRACT]](s16)
+    ; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s8)
+    ; CHECK: $vgpr0 = COPY [[ANYEXT1]](s32)
     %0:_(<4 x s8>) = G_IMPLICIT_DEF
     %1:_(s8) = G_EXTRACT %0, 24
     %2:_(s32) = G_ANYEXT %1
@@ -179,10 +191,13 @@
 body: |
   bb.0:
     ; CHECK-LABEL: name: extract_s8_v3s8_offset16
-    ; CHECK: [[DEF:%[0-9]+]]:_(<3 x s16>) = G_IMPLICIT_DEF
-    ; CHECK: [[EXTRACT:%[0-9]+]]:_(s16) = G_EXTRACT [[DEF]](<3 x s16>), 32
-    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[EXTRACT]](s16)
-    ; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)
+    ; CHECK: [[DEF:%[0-9]+]]:_(<3 x s32>) = G_IMPLICIT_DEF
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(<3 x s8>) = G_TRUNC [[DEF]](<3 x s32>)
+    ; CHECK: [[ANYEXT:%[0-9]+]]:_(<3 x s16>) = G_ANYEXT [[TRUNC]](<3 x s8>)
+    ; CHECK: [[EXTRACT:%[0-9]+]]:_(s16) = G_EXTRACT [[ANYEXT]](<3 x s16>), 32
+    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[EXTRACT]](s16)
+    ; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s8)
+    ; CHECK: $vgpr0 = COPY [[ANYEXT1]](s32)
     %0:_(<3 x s8>) = G_IMPLICIT_DEF
     %1:_(s8) = G_EXTRACT %0, 16
     %2:_(s32) = G_ANYEXT %1
@@ -196,10 +211,13 @@
 body: |
   bb.0:
     ; CHECK-LABEL: name: extract_s8_v5s1_offset4
-    ; CHECK: [[DEF:%[0-9]+]]:_(<5 x s16>) = G_IMPLICIT_DEF
-    ; CHECK: [[EXTRACT:%[0-9]+]]:_(s16) = G_EXTRACT [[DEF]](<5 x s16>), 80
-    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[EXTRACT]](s16)
-    ; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)
+    ; CHECK: [[DEF:%[0-9]+]]:_(<5 x s32>) = G_IMPLICIT_DEF
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(<5 x s1>) = G_TRUNC [[DEF]](<5 x s32>)
+    ; CHECK: [[ANYEXT:%[0-9]+]]:_(<5 x s16>) = G_ANYEXT [[TRUNC]](<5 x s1>)
+    ; CHECK: [[EXTRACT:%[0-9]+]]:_(s16) = G_EXTRACT [[ANYEXT]](<5 x s16>), 80
+    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s1) = G_TRUNC [[EXTRACT]](s16)
+    ; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s1)
+    ; CHECK: $vgpr0 = COPY [[ANYEXT1]](s32)
     %0:_(<5 x s1>) = G_IMPLICIT_DEF
     %1:_(s1) = G_EXTRACT %0, 5
     %2:_(s32) = G_ANYEXT %1
@@ -228,8 +246,9 @@
 body: |
   bb.0:
     ; CHECK-LABEL: name: extract_v2s16_v6s16_offset32
-    ; CHECK: [[DEF:%[0-9]+]]:_(<6 x s16>) = G_IMPLICIT_DEF
-    ; CHECK: [[EXTRACT:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[DEF]](<6 x s16>), 32
+    ; CHECK: [[DEF:%[0-9]+]]:_(<6 x s32>) = G_IMPLICIT_DEF
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(<6 x s16>) = G_TRUNC [[DEF]](<6 x s32>)
+    ; CHECK: [[EXTRACT:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[TRUNC]](<6 x s16>), 32
     ; CHECK: $vgpr0 = COPY [[EXTRACT]](<2 x s16>)
     %0:_(<6 x s16>) = G_IMPLICIT_DEF
     %1:_(<2 x s16>) = G_EXTRACT %0, 32
diff --git a/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def.mir b/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def.mir
index df7e40e..786ec13 100644
--- a/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def.mir
+++ b/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def.mir
@@ -1,16 +1,116 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -run-pass=legalizer %s -o - | FileCheck %s
-
-# FIXME: Need to add test for IMPLICIT_DEF > 512 once all the operations used
-# to legalize IMPLICIT_DEF are leagl.
+# RUN: llc -O0 -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck %s
+# RUN: llc -O0 -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck %s
 
 ---
-name:            test_implicit_def
+name: test_implicit_def_s1
 body: |
   bb.0:
-    liveins: $vgpr0, $vgpr1
 
-    ; CHECK-LABEL: name: test_implicit_def
+    ; CHECK-LABEL: name: test_implicit_def_s1
+    ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+    ; CHECK: $vgpr0 = COPY [[DEF]](s32)
+    %0:_(s1) = G_IMPLICIT_DEF
+    %1:_(s32) = G_ANYEXT %0
+    $vgpr0 = COPY %1
+...
+
+---
+name: test_implicit_def_s7
+body: |
+  bb.0:
+
+    ; CHECK-LABEL: name: test_implicit_def_s7
+    ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+    ; CHECK: $vgpr0 = COPY [[COPY]](s32)
+    %0:_(s7) = G_IMPLICIT_DEF
+    %1:_(s32) = G_ANYEXT %0
+    $vgpr0 = COPY %1
+...
+
+---
+name: test_implicit_def_s8
+body: |
+  bb.0:
+
+    ; CHECK-LABEL: name: test_implicit_def_s8
+    ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+    ; CHECK: $vgpr0 = COPY [[COPY]](s32)
+    %0:_(s8) = G_IMPLICIT_DEF
+    %1:_(s32) = G_ANYEXT %0
+    $vgpr0 = COPY %1
+...
+
+---
+name: test_implicit_def_s16
+body: |
+  bb.0:
+
+    ; CHECK-LABEL: name: test_implicit_def_s16
+    ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+    ; CHECK: $vgpr0 = COPY [[COPY]](s32)
+    %0:_(s16) = G_IMPLICIT_DEF
+    %1:_(s32) = G_ANYEXT %0
+    $vgpr0 = COPY %1
+...
+
+---
+name: test_implicit_def_s32
+body: |
+  bb.0:
+
+    ; CHECK-LABEL: name: test_implicit_def_s32
+    ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+    ; CHECK: $vgpr0 = COPY [[DEF]](s32)
+    %0:_(s32) = G_IMPLICIT_DEF
+    $vgpr0 = COPY %0
+...
+
+---
+name: test_implicit_def_s64
+body: |
+  bb.0:
+
+    ; CHECK-LABEL: name: test_implicit_def_s64
+    ; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+    ; CHECK: $vgpr0_vgpr1 = COPY [[DEF]](s64)
+    %0:_(s64) = G_IMPLICIT_DEF
+    $vgpr0_vgpr1 = COPY %0
+...
+
+---
+name: test_implicit_def_s128
+body: |
+  bb.0:
+
+    ; CHECK-LABEL: name: test_implicit_def_s128
+    ; CHECK: [[DEF:%[0-9]+]]:_(s128) = G_IMPLICIT_DEF
+    ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[DEF]](s128)
+    %0:_(s128) = G_IMPLICIT_DEF
+    $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %0
+...
+
+---
+name: test_implicit_def_256
+body: |
+  bb.0:
+
+    ; CHECK-LABEL: name: test_implicit_def_256
+    ; CHECK: [[DEF:%[0-9]+]]:_(s256) = G_IMPLICIT_DEF
+    ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[DEF]](s256)
+    %0:_(s256) = G_IMPLICIT_DEF
+    $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY %0
+...
+
+---
+name: test_implicit_def_s448
+body: |
+  bb.0:
+
+    ; CHECK-LABEL: name: test_implicit_def_s448
     ; CHECK: [[DEF:%[0-9]+]]:_(s448) = G_IMPLICIT_DEF
     ; CHECK: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[DEF]](s448), 0
     ; CHECK: $vgpr0 = COPY [[EXTRACT]](s32)
@@ -18,3 +118,244 @@
     %1:_(s32) = G_EXTRACT %0, 0
     $vgpr0 = COPY %1
 ...
+
+---
+name: test_implicit_def_s512
+body: |
+  bb.0:
+
+    ; CHECK-LABEL: name: test_implicit_def_s512
+    ; CHECK: [[DEF:%[0-9]+]]:_(s512) = G_IMPLICIT_DEF
+    ; CHECK: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[DEF]](s512), 0
+    ; CHECK: $vgpr0 = COPY [[EXTRACT]](s32)
+    %0:_(s512) = G_IMPLICIT_DEF
+    %1:_(s32) = G_EXTRACT %0, 0
+    $vgpr0 = COPY %1
+...
+
+---
+name: test_implicit_def_s1024
+body: |
+  bb.0:
+
+    ; CHECK-LABEL: name: test_implicit_def_s1024
+    ; CHECK: [[DEF:%[0-9]+]]:_(s512) = G_IMPLICIT_DEF
+    ; CHECK: [[DEF1:%[0-9]+]]:_(s512) = G_IMPLICIT_DEF
+    ; CHECK: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[DEF]](s512), 0
+    ; CHECK: $vgpr0 = COPY [[EXTRACT]](s32)
+    %0:_(s1024) = G_IMPLICIT_DEF
+    %1:_(s32) = G_EXTRACT %0, 0
+    $vgpr0 = COPY %1
+...
+
+---
+name: test_implicit_def_v2s32
+body: |
+  bb.0:
+
+    ; CHECK-LABEL: name: test_implicit_def_v2s32
+    ; CHECK: [[DEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
+    ; CHECK: $vgpr0_vgpr1 = COPY [[DEF]](<2 x s32>)
+    %0:_(<2 x s32>) = G_IMPLICIT_DEF
+    $vgpr0_vgpr1 = COPY %0
+...
+
+---
+name: test_implicit_def_v3s32
+body: |
+  bb.0:
+
+    ; CHECK-LABEL: name: test_implicit_def_v3s32
+    ; CHECK: [[DEF:%[0-9]+]]:_(<3 x s32>) = G_IMPLICIT_DEF
+    ; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[DEF]](<3 x s32>)
+    %0:_(<3 x s32>) = G_IMPLICIT_DEF
+    $vgpr0_vgpr1_vgpr2 = COPY %0
+...
+
+---
+name: test_implicit_def_v4s32
+body: |
+  bb.0:
+
+    ; CHECK-LABEL: name: test_implicit_def_v4s32
+    ; CHECK: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
+    ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[DEF]](<4 x s32>)
+    %0:_(<4 x s32>) = G_IMPLICIT_DEF
+    $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %0
+...
+
+---
+name: test_implicit_def_v2s1
+body: |
+  bb.0:
+
+    ; CHECK-LABEL: name: test_implicit_def_v2s1
+    ; CHECK: [[DEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
+    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY [[DEF]](<2 x s32>)
+    ; CHECK: $vgpr0_vgpr1 = COPY [[COPY]](<2 x s32>)
+    %0:_(<2 x s1>) = G_IMPLICIT_DEF
+    %1:_(<2 x s32>) = G_ANYEXT %0
+    $vgpr0_vgpr1 = COPY %1
+...
+
+---
+name: test_implicit_def_v2s16
+body: |
+  bb.0:
+
+    ; CHECK-LABEL: name: test_implicit_def_v2s16
+    ; CHECK: [[DEF:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
+    ; CHECK: $vgpr0 = COPY [[DEF]](<2 x s16>)
+    %0:_(<2 x s16>) = G_IMPLICIT_DEF
+    $vgpr0 = COPY %0
+...
+
+---
+name: test_implicit_def_v3s16
+body: |
+  bb.0:
+
+    ; CHECK-LABEL: name: test_implicit_def_v3s16
+    ; CHECK: [[DEF:%[0-9]+]]:_(<3 x s16>) = G_IMPLICIT_DEF
+    ; CHECK: [[DEF1:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
+    ; CHECK: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF1]], [[DEF]](<3 x s16>), 0
+    ; CHECK: $vgpr0_vgpr1 = COPY [[INSERT]](<4 x s16>)
+    %0:_(<3 x s16>) = G_IMPLICIT_DEF
+    %1:_(<4 x s16>) = G_IMPLICIT_DEF
+    %2:_(<4 x s16>) = G_INSERT %1, %0, 0
+    $vgpr0_vgpr1 = COPY %2
+...
+
+---
+name: test_implicit_def_v4s16
+body: |
+  bb.0:
+
+    ; CHECK-LABEL: name: test_implicit_def_v4s16
+    ; CHECK: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
+    ; CHECK: $vgpr0_vgpr1 = COPY [[DEF]](<4 x s16>)
+    %0:_(<4 x s16>) = G_IMPLICIT_DEF
+    $vgpr0_vgpr1 = COPY %0
+...
+
+---
+name: test_implicit_def_v8s16
+body: |
+  bb.0:
+
+    ; CHECK-LABEL: name: test_implicit_def_v8s16
+    ; CHECK: [[DEF:%[0-9]+]]:_(<8 x s32>) = G_IMPLICIT_DEF
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(<8 x s16>) = G_TRUNC [[DEF]](<8 x s32>)
+    ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[TRUNC]](<8 x s16>)
+    %0:_(<8 x s16>) = G_IMPLICIT_DEF
+    $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %0
+...
+
+---
+name: test_implicit_def_v2s64
+body: |
+  bb.0:
+
+    ; CHECK-LABEL: name: test_implicit_def_v2s64
+    ; CHECK: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
+    ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[DEF]](<2 x s64>)
+    %0:_(<2 x s64>) = G_IMPLICIT_DEF
+    $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %0
+...
+
+---
+name: test_implicit_def_v4s8
+body: |
+  bb.0:
+
+    ; CHECK-LABEL: name: test_implicit_def_v4s8
+    ; CHECK: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[DEF]](<4 x s32>)
+    ; CHECK: $vgpr0 = COPY [[TRUNC]](<4 x s8>)
+    %0:_(<4 x s8>) = G_IMPLICIT_DEF
+    $vgpr0 = COPY %0
+...
+
+---
+name: test_implicit_def_p0
+body: |
+  bb.0:
+
+    ; CHECK-LABEL: name: test_implicit_def_p0
+    ; CHECK: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
+    ; CHECK: $vgpr0_vgpr1 = COPY [[DEF]](p0)
+    %0:_(p0) = G_IMPLICIT_DEF
+    $vgpr0_vgpr1 = COPY %0
+...
+
+---
+name: test_implicit_def_p1
+body: |
+  bb.0:
+
+    ; CHECK-LABEL: name: test_implicit_def_p1
+    ; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
+    ; CHECK: $vgpr0_vgpr1 = COPY [[DEF]](p1)
+    %0:_(p1) = G_IMPLICIT_DEF
+    $vgpr0_vgpr1 = COPY %0
+...
+
+---
+name: test_implicit_def_p2
+body: |
+  bb.0:
+
+    ; CHECK-LABEL: name: test_implicit_def_p2
+    ; CHECK: [[DEF:%[0-9]+]]:_(p2) = G_IMPLICIT_DEF
+    ; CHECK: $vgpr0 = COPY [[DEF]](p2)
+    %0:_(p2) = G_IMPLICIT_DEF
+    $vgpr0 = COPY %0
+...
+
+---
+name: test_implicit_def_p3
+body: |
+  bb.0:
+
+    ; CHECK-LABEL: name: test_implicit_def_p3
+    ; CHECK: [[DEF:%[0-9]+]]:_(p3) = G_IMPLICIT_DEF
+    ; CHECK: $vgpr0 = COPY [[DEF]](p3)
+    %0:_(p3) = G_IMPLICIT_DEF
+    $vgpr0 = COPY %0
+...
+
+---
+name: test_implicit_def_p4
+body: |
+  bb.0:
+
+    ; CHECK-LABEL: name: test_implicit_def_p4
+    ; CHECK: [[DEF:%[0-9]+]]:_(p4) = G_IMPLICIT_DEF
+    ; CHECK: $vgpr0_vgpr1 = COPY [[DEF]](p4)
+    %0:_(p4) = G_IMPLICIT_DEF
+    $vgpr0_vgpr1 = COPY %0
+...
+
+---
+name: test_implicit_def_p5
+body: |
+  bb.0:
+
+    ; CHECK-LABEL: name: test_implicit_def_p5
+    ; CHECK: [[DEF:%[0-9]+]]:_(p5) = G_IMPLICIT_DEF
+    ; CHECK: $vgpr0 = COPY [[DEF]](p5)
+    %0:_(p5) = G_IMPLICIT_DEF
+    $vgpr0 = COPY %0
+...
+
+---
+name: test_implicit_def_p999
+body: |
+  bb.0:
+
+    ; CHECK-LABEL: name: test_implicit_def_p999
+    ; CHECK: [[DEF:%[0-9]+]]:_(p999) = G_IMPLICIT_DEF
+    ; CHECK: $vgpr0_vgpr1 = COPY [[DEF]](p999)
+    %0:_(p999) = G_IMPLICIT_DEF
+    $vgpr0_vgpr1 = COPY %0
+...