[SystemZ] Regenerate tests to make complete codegen more obvious
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356137 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/test/CodeGen/SystemZ/buildvector-00.ll b/test/CodeGen/SystemZ/buildvector-00.ll
index dc1c0ff..463da06 100644
--- a/test/CodeGen/SystemZ/buildvector-00.ll
+++ b/test/CodeGen/SystemZ/buildvector-00.ll
@@ -1,12 +1,23 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
; Test that the dag combiner can understand that some vector operands are
; all-zeros and then optimize the logical operations.
-;
-; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
define void @f1() {
; CHECK-LABEL: f1:
-; CHECK: vno
-; CHECK-NOT: vno
+; CHECK: # %bb.0: # %bb
+; CHECK-NEXT: vlrepg %v0, 0(%r1)
+; CHECK-NEXT: vgbm %v1, 0
+; CHECK-NEXT: vceqg %v2, %v0, %v1
+; CHECK-NEXT: vn %v0, %v0, %v0
+; CHECK-NEXT: vno %v2, %v2, %v2
+; CHECK-NEXT: vceqg %v0, %v0, %v1
+; CHECK-NEXT: vx %v0, %v2, %v0
+; CHECK-NEXT: vnc %v0, %v2, %v0
+; CHECK-NEXT: vlgvf %r0, %v0, 1
+; CHECK-NEXT: tmll %r0, 1
+; CHECK-NEXT: # %bb.1: # %bb15
bb:
%tmp = shufflevector <2 x i64> undef, <2 x i64> undef, <2 x i32> zeroinitializer
diff --git a/test/CodeGen/SystemZ/dag-combine-03.ll b/test/CodeGen/SystemZ/dag-combine-03.ll
index c197c9a..379d53a 100644
--- a/test/CodeGen/SystemZ/dag-combine-03.ll
+++ b/test/CodeGen/SystemZ/dag-combine-03.ll
@@ -1,9 +1,36 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 < %s | FileCheck %s
+
; Test that DAGCombiner gets helped by getKnownBitsForTargetNode() when
; BITCAST nodes are involved on a big-endian target.
;
-; RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 < %s | FileCheck %s
+; The EXTRACT_VECTOR_ELT is done first into an i32, and then AND:ed with
+; 1. The AND is not actually necessary since the element contains a CC (i1)
+; value. Test that the BITCAST nodes in the DAG when computing KnownBits is
+; handled so that the AND is removed. If this succeeds, this results in a CHI
+; instead of TMLL.
define void @fun() {
+; CHECK-LABEL: fun:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lghi %r1, 0
+; CHECK-NEXT: .LBB0_1: # %lab0
+; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: la %r0, 2(%r1)
+; CHECK-NEXT: la %r1, 1(%r1)
+; CHECK-NEXT: cgr %r1, %r0
+; CHECK-NEXT: lhi %r2, 0
+; CHECK-NEXT: lochie %r2, 1
+; CHECK-NEXT: cgr %r0, %r0
+; CHECK-NEXT: lhi %r0, 0
+; CHECK-NEXT: lochie %r0, 1
+; CHECK-NEXT: vlvgp %v0, %r2, %r2
+; CHECK-NEXT: vlvgp %v1, %r0, %r0
+; CHECK-NEXT: vx %v0, %v0, %v1
+; CHECK-NEXT: vlgvf %r0, %v0, 1
+; CHECK-NEXT: chi %r0, 0
+; CHECK-NEXT: locghie %r1, 0
+; CHECK-NEXT: j .LBB0_1
entry:
br label %lab0
@@ -17,16 +44,7 @@
%ins2 = insertelement <2 x i1> undef, i1 %cmp2, i32 0
%xor = xor <2 x i1> %ins, %ins2
%extr = extractelement <2 x i1> %xor, i32 0
-; The EXTRACT_VECTOR_ELT is done first into an i32, and then AND:ed with
-; 1. The AND is not actually necessary since the element contains a CC (i1)
-; value. Test that the BITCAST nodes in the DAG when computing KnownBits is
-; handled so that the AND is removed. If this succeeds, this results in a CHI
-; instead of TMLL.
-; CHECK-LABEL: # %bb.0:
-; CHECK: chi
-; CHECK-NOT: tmll
-; CHECK: j
%sel = select i1 %extr, i64 %add, i64 0
br label %lab0
}
