llvm /
llvm /
bc20418018b2ee0025cb1e33b4d2fb7bf2e8ddaa [MIPS GlobalISel] Add MSA registers to fprb. Select vector load, store
Add vector MSA register classes to fprb, they are 128 bit wide.
MSA instructions use the same registers for both integer and floating
point operations. Therefore we only need to check for vector element
size during legalization or instruction selection.
Add helper function in MipsLegalizerInfo and switch to legalIf
LegalizeRuleSet to keep legalization rules compact since they depend
on MipsSubtarget and presence of MSA.
fprb is assigned to all vector operands.
Move selectLoadStoreOpCode to MipsInstructionSelector in order to
reduce number of arguments.
Differential Revision: https://reviews.llvm.org/D68867
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@374872 91177308-0d34-0410-b5e6-96231b3b80d8
8 files changed
