Recommit "[PowerPC] Fix assert from machine verify pass that unmatched register class about fcmp selection in fast-isel"
This re-commit r350685.
Differential Revision: https://reviews.llvm.org/D55686
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350799 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/PowerPC/PPCFastISel.cpp b/lib/Target/PowerPC/PPCFastISel.cpp
index aa55ac1..3b2d92d 100644
--- a/lib/Target/PowerPC/PPCFastISel.cpp
+++ b/lib/Target/PowerPC/PPCFastISel.cpp
@@ -861,8 +861,20 @@
}
}
+ unsigned SrcReg1 = getRegForValue(SrcValue1);
+ if (SrcReg1 == 0)
+ return false;
+
+ unsigned SrcReg2 = 0;
+ if (!UseImm) {
+ SrcReg2 = getRegForValue(SrcValue2);
+ if (SrcReg2 == 0)
+ return false;
+ }
+
unsigned CmpOpc;
bool NeedsExt = false;
+ auto RC = MRI.getRegClass(SrcReg1);
switch (SrcVT.SimpleTy) {
default: return false;
case MVT::f32:
@@ -879,8 +891,15 @@
CmpOpc = PPC::EFSCMPGT;
break;
}
- } else
+ } else {
CmpOpc = PPC::FCMPUS;
+ if (isVSSRCRegClass(RC)) {
+ unsigned TmpReg = createResultReg(&PPC::F4RCRegClass);
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
+ TII.get(TargetOpcode::COPY), TmpReg).addReg(SrcReg1);
+ SrcReg1 = TmpReg;
+ }
+ }
break;
case MVT::f64:
if (HasSPE) {
@@ -896,8 +915,11 @@
CmpOpc = PPC::EFDCMPGT;
break;
}
- } else
+ } else if (isVSFRCRegClass(RC)) {
+ CmpOpc = PPC::XSCMPUDP;
+ } else {
CmpOpc = PPC::FCMPUD;
+ }
break;
case MVT::i1:
case MVT::i8:
@@ -918,17 +940,6 @@
break;
}
- unsigned SrcReg1 = getRegForValue(SrcValue1);
- if (SrcReg1 == 0)
- return false;
-
- unsigned SrcReg2 = 0;
- if (!UseImm) {
- SrcReg2 = getRegForValue(SrcValue2);
- if (SrcReg2 == 0)
- return false;
- }
-
if (NeedsExt) {
unsigned ExtReg = createResultReg(&PPC::GPRCRegClass);
if (!PPCEmitIntExt(SrcVT, SrcReg1, MVT::i32, ExtReg, IsZExt))
diff --git a/test/CodeGen/PowerPC/fast-isel-fcmp-nan.ll b/test/CodeGen/PowerPC/fast-isel-fcmp-nan.ll
index f060395..84d4614 100644
--- a/test/CodeGen/PowerPC/fast-isel-fcmp-nan.ll
+++ b/test/CodeGen/PowerPC/fast-isel-fcmp-nan.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple powerpc64le-unknown-linux-gnu -fast-isel -O0 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple powerpc64le-unknown-linux-gnu -fast-isel -O0 < %s | FileCheck %s
define i1 @TestULT(double %t0) {
; CHECK-LABEL: TestULT:
@@ -17,7 +17,7 @@
define i1 @TestULE(double %t0) {
; CHECK-LABEL: TestULE:
-; CHECK: fcmpu
+; CHECK: xscmpudp
; CHECK-NEXT: ble
; CHECK: blr
entry:
@@ -33,7 +33,7 @@
define i1 @TestUNE(double %t0) {
; CHECK-LABEL: TestUNE:
-; CHECK: fcmpu
+; CHECK: xscmpudp
; CHECK-NEXT: bne
; CHECK: blr
entry:
@@ -79,7 +79,7 @@
define i1 @TestUGE(double %t0) {
; CHECK-LABEL: TestUGE:
-; CHECK: fcmpu
+; CHECK: xscmpudp
; CHECK-NEXT: bge
; CHECK: blr
entry:
@@ -95,7 +95,7 @@
define i1 @TestOLT(double %t0) {
; CHECK-LABEL: TestOLT:
-; CHECK: fcmpu
+; CHECK: xscmpudp
; CHECK-NEXT: blt
; CHECK: blr
entry:
@@ -141,7 +141,7 @@
define i1 @TestOEQ(double %t0) {
; CHECK-LABEL: TestOEQ:
-; CHECK: fcmpu
+; CHECK: xscmpudp
; CHECK-NEXT: beq
; CHECK: blr
entry:
@@ -157,7 +157,7 @@
define i1 @TestOGT(double %t0) {
; CHECK-LABEL: TestOGT:
-; CHECK: fcmpu
+; CHECK: xscmpudp
; CHECK-NEXT: bgt
; CHECK: blr
entry:
diff --git a/test/CodeGen/PowerPC/vsx-self-copy.ll b/test/CodeGen/PowerPC/vsx-self-copy.ll
index 787ac4b..6a6008d 100644
--- a/test/CodeGen/PowerPC/vsx-self-copy.ll
+++ b/test/CodeGen/PowerPC/vsx-self-copy.ll
@@ -1,5 +1,5 @@
-; RUN: llc -mcpu=pwr7 -mattr=+vsx < %s | FileCheck %s
-; RUN: llc -mcpu=pwr7 -mattr=+vsx -fast-isel -O0 < %s | FileCheck %s
+; RUN: llc -mcpu=pwr7 -mattr=+vsx < %s -verify-machineinstrs | FileCheck %s
+; RUN: llc -mcpu=pwr7 -mattr=+vsx -fast-isel -O0 < %s -verify-machineinstrs | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu"
