commit b1407138d45ba368aefd73f33ecb25f09432531a
author Simon Pilgrim <llvm-dev@redking.me.uk> Mon Oct 21 19:19:50 2019 +0000
committer Simon Pilgrim <llvm-dev@redking.me.uk> Mon Oct 21 19:19:50 2019 +0000
tree 87ff4b7a3a9a111862f89f8ab6ab98014b53a4de
parent f5e25f84faff6c548ca1a767269cc0e32dc34095

[X86] Rename matchBitOpReduction to matchScalarReduction. NFCI.

This doesn't need to be just for bitops, but the ops do need to be fully associative.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375445 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/X86/X86ISelLowering.cpp

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 5211b1b..8905b89 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -19891,8 +19891,8 @@
 
 /// Helper for matching OR(EXTRACTELT(X,0),OR(EXTRACTELT(X,1),...))
 /// style scalarized (associative) reduction patterns.
-static bool matchBitOpReduction(SDValue Op, ISD::NodeType BinOp,
-                                SmallVectorImpl<SDValue> &SrcOps) {
+static bool matchScalarReduction(SDValue Op, ISD::NodeType BinOp,
+                                 SmallVectorImpl<SDValue> &SrcOps) {
   SmallVector<SDValue, 8> Opnds;
   DenseMap<SDValue, APInt> SrcOpMap;
   EVT VT = MVT::Other;
@@ -19965,7 +19965,7 @@
     return SDValue();
 
   SmallVector<SDValue, 8> VecIns;
-  if (!matchBitOpReduction(Op, ISD::OR, VecIns))
+  if (!matchScalarReduction(Op, ISD::OR, VecIns))
     return SDValue();
 
   // Quit if not 128/256-bit vector.
@@ -39129,7 +39129,7 @@
   // TODO: Support multiple SrcOps.
   if (VT == MVT::i1) {
     SmallVector<SDValue, 2> SrcOps;
-    if (matchBitOpReduction(SDValue(N, 0), ISD::AND, SrcOps) &&
+    if (matchScalarReduction(SDValue(N, 0), ISD::AND, SrcOps) &&
         SrcOps.size() == 1) {
       SDLoc dl(N);
       unsigned NumElts = SrcOps[0].getValueType().getVectorNumElements();