diff --git a/lib/Target/Mips/MicroMips32r6InstrInfo.td b/lib/Target/Mips/MicroMips32r6InstrInfo.td
index 61f54ca..dd86ba7 100644
--- a/lib/Target/Mips/MicroMips32r6InstrInfo.td
+++ b/lib/Target/Mips/MicroMips32r6InstrInfo.td
@@ -245,6 +245,7 @@
 class MSUBF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.s", 0, 0b111111000>;
 class MSUBF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.d", 1, 0b111111000>;
 class FMOV_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.s", 0, 0b0000001>;
+class FMOV_D_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.d", 1, 0b0000001>;
 class FNEG_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"neg.s", 0, 0b0101101>;
 class MAX_S_MMR6_ENC : POOL32F_MINMAX_FM<"max.s", 0, 0b000001011>;
 class MAX_D_MMR6_ENC : POOL32F_MINMAX_FM<"max.d", 1, 0b000001011>;
@@ -889,6 +890,8 @@
 }
 class FMOV_S_MMR6_DESC
   : FMOV_FNEG_MMR6_DESC_BASE<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>;
+class FMOV_D_MMR6_DESC
+  : FMOV_FNEG_MMR6_DESC_BASE<"mov.d", FGR64Opnd, FGR64Opnd, II_MOV_D>;
 class FNEG_S_MMR6_DESC
   : FMOV_FNEG_MMR6_DESC_BASE<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>;
 
@@ -1461,6 +1464,8 @@
                    ISA_MICROMIPS32R6;
 def FMOV_S_MMR6 : StdMMR6Rel, FMOV_S_MMR6_ENC, FMOV_S_MMR6_DESC,
                   ISA_MICROMIPS32R6;
+def FMOV_D_MMR6 : StdMMR6Rel, FMOV_D_MMR6_ENC, FMOV_D_MMR6_DESC,
+                  ISA_MICROMIPS32R6;
 def FNEG_S_MMR6 : StdMMR6Rel, FNEG_S_MMR6_ENC, FNEG_S_MMR6_DESC,
                   ISA_MICROMIPS32R6;
 def MAX_S_MMR6 : R6MMR6Rel, MAX_S_MMR6_ENC, MAX_S_MMR6_DESC, ISA_MICROMIPS32R6;
diff --git a/lib/Target/Mips/MicroMipsInstrFPU.td b/lib/Target/Mips/MicroMipsInstrFPU.td
index c97dae9..2fdc489 100644
--- a/lib/Target/Mips/MicroMipsInstrFPU.td
+++ b/lib/Target/Mips/MicroMipsInstrFPU.td
@@ -113,8 +113,7 @@
                 ISA_MICROMIPS, FGR_32 {
     string DecoderNamespace = "MicroMips";
   }
-  // FIXME: This needs to be part of the instruction mapping tables.
-  def _D64_MM : ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>,
+  def _D64_MM : StdMMR6Rel, ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>,
                 ISA_MICROMIPS, FGR_64 {
     string DecoderNamespace = "MicroMipsFP64";
   }
diff --git a/lib/Target/Mips/MipsInstrFPU.td b/lib/Target/Mips/MipsInstrFPU.td
index 0b03da9..549bce2 100644
--- a/lib/Target/Mips/MipsInstrFPU.td
+++ b/lib/Target/Mips/MipsInstrFPU.td
@@ -142,7 +142,7 @@
                   SDPatternOperator OpNode= null_frag> {
   def _D32 : MMRel, ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, Itin, OpNode>,
              FGR_32;
-  def _D64 : ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>, FGR_64 {
+  def _D64 : StdMMR6Rel, ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>, FGR_64 {
     string DecoderNamespace = "MipsFP64";
   }
 }
diff --git a/test/CodeGen/Mips/llvm-ir/fptosi.ll b/test/CodeGen/Mips/llvm-ir/fptosi.ll
index 45517c1..537e2d9 100644
--- a/test/CodeGen/Mips/llvm-ir/fptosi.ll
+++ b/test/CodeGen/Mips/llvm-ir/fptosi.ll
@@ -38,23 +38,23 @@
 define i32 @test1(float %t) {
 ; M32-LABEL: test1:
 ; M32:       # %bb.0: # %entry
-; M32-NEXT:    trunc.w.s $f0, $f12 # <MCInst #2637 TRUNC_W_S
+; M32-NEXT:    trunc.w.s $f0, $f12 # <MCInst #2638 TRUNC_W_S
 ; M32-NEXT:    # <MCOperand Reg:147>
 ; M32-NEXT:    # <MCOperand Reg:159>>
-; M32-NEXT:    jr $ra # <MCInst #1628 JR
+; M32-NEXT:    jr $ra # <MCInst #1629 JR
 ; M32-NEXT:    # <MCOperand Reg:19>>
-; M32-NEXT:    mfc1 $2, $f0 # <MCInst #1837 MFC1
+; M32-NEXT:    mfc1 $2, $f0 # <MCInst #1838 MFC1
 ; M32-NEXT:    # <MCOperand Reg:321>
 ; M32-NEXT:    # <MCOperand Reg:147>>
 ;
 ; M32R2-FP64-LABEL: test1:
 ; M32R2-FP64:       # %bb.0: # %entry
-; M32R2-FP64-NEXT:    trunc.w.s $f0, $f12 # <MCInst #2637 TRUNC_W_S
+; M32R2-FP64-NEXT:    trunc.w.s $f0, $f12 # <MCInst #2638 TRUNC_W_S
 ; M32R2-FP64-NEXT:    # <MCOperand Reg:147>
 ; M32R2-FP64-NEXT:    # <MCOperand Reg:159>>
-; M32R2-FP64-NEXT:    jr $ra # <MCInst #1628 JR
+; M32R2-FP64-NEXT:    jr $ra # <MCInst #1629 JR
 ; M32R2-FP64-NEXT:    # <MCOperand Reg:19>>
-; M32R2-FP64-NEXT:    mfc1 $2, $f0 # <MCInst #1837 MFC1
+; M32R2-FP64-NEXT:    mfc1 $2, $f0 # <MCInst #1838 MFC1
 ; M32R2-FP64-NEXT:    # <MCOperand Reg:321>
 ; M32R2-FP64-NEXT:    # <MCOperand Reg:147>>
 ;
@@ -66,23 +66,23 @@
 ; M32R2-SF-NEXT:    # <MCOperand Imm:-24>>
 ; M32R2-SF-NEXT:    .cfi_def_cfa_offset 24
 ; M32R2-SF-NEXT:    sw $ra, 20($sp) # 4-byte Folded Spill
-; M32R2-SF-NEXT:    # <MCInst #2519 SW
+; M32R2-SF-NEXT:    # <MCInst #2520 SW
 ; M32R2-SF-NEXT:    # <MCOperand Reg:19>
 ; M32R2-SF-NEXT:    # <MCOperand Reg:20>
 ; M32R2-SF-NEXT:    # <MCOperand Imm:20>>
 ; M32R2-SF-NEXT:    .cfi_offset 31, -4
-; M32R2-SF-NEXT:    jal __fixsfsi # <MCInst #1606 JAL
+; M32R2-SF-NEXT:    jal __fixsfsi # <MCInst #1607 JAL
 ; M32R2-SF-NEXT:    # <MCOperand Expr:(__fixsfsi)>>
-; M32R2-SF-NEXT:    nop # <MCInst #2370 SLL
+; M32R2-SF-NEXT:    nop # <MCInst #2371 SLL
 ; M32R2-SF-NEXT:    # <MCOperand Reg:21>
 ; M32R2-SF-NEXT:    # <MCOperand Reg:21>
 ; M32R2-SF-NEXT:    # <MCOperand Imm:0>>
 ; M32R2-SF-NEXT:    lw $ra, 20($sp) # 4-byte Folded Reload
-; M32R2-SF-NEXT:    # <MCInst #1722 LW
+; M32R2-SF-NEXT:    # <MCInst #1723 LW
 ; M32R2-SF-NEXT:    # <MCOperand Reg:19>
 ; M32R2-SF-NEXT:    # <MCOperand Reg:20>
 ; M32R2-SF-NEXT:    # <MCOperand Imm:20>>
-; M32R2-SF-NEXT:    jr $ra # <MCInst #1628 JR
+; M32R2-SF-NEXT:    jr $ra # <MCInst #1629 JR
 ; M32R2-SF-NEXT:    # <MCOperand Reg:19>>
 ; M32R2-SF-NEXT:    addiu $sp, $sp, 24 # <MCInst #624 ADDiu
 ; M32R2-SF-NEXT:    # <MCOperand Reg:20>
@@ -91,69 +91,69 @@
 ;
 ; M32R3R5-LABEL: test1:
 ; M32R3R5:       # %bb.0: # %entry
-; M32R3R5-NEXT:    trunc.w.s $f0, $f12 # <MCInst #2637 TRUNC_W_S
+; M32R3R5-NEXT:    trunc.w.s $f0, $f12 # <MCInst #2638 TRUNC_W_S
 ; M32R3R5-NEXT:    # <MCOperand Reg:147>
 ; M32R3R5-NEXT:    # <MCOperand Reg:159>>
-; M32R3R5-NEXT:    jr $ra # <MCInst #1628 JR
+; M32R3R5-NEXT:    jr $ra # <MCInst #1629 JR
 ; M32R3R5-NEXT:    # <MCOperand Reg:19>>
-; M32R3R5-NEXT:    mfc1 $2, $f0 # <MCInst #1837 MFC1
+; M32R3R5-NEXT:    mfc1 $2, $f0 # <MCInst #1838 MFC1
 ; M32R3R5-NEXT:    # <MCOperand Reg:321>
 ; M32R3R5-NEXT:    # <MCOperand Reg:147>>
 ;
 ; M32R6-LABEL: test1:
 ; M32R6:       # %bb.0: # %entry
-; M32R6-NEXT:    trunc.w.s $f0, $f12 # <MCInst #2637 TRUNC_W_S
+; M32R6-NEXT:    trunc.w.s $f0, $f12 # <MCInst #2638 TRUNC_W_S
 ; M32R6-NEXT:    # <MCOperand Reg:147>
 ; M32R6-NEXT:    # <MCOperand Reg:159>>
-; M32R6-NEXT:    jr $ra # <MCInst #1607 JALR
+; M32R6-NEXT:    jr $ra # <MCInst #1608 JALR
 ; M32R6-NEXT:    # <MCOperand Reg:21>
 ; M32R6-NEXT:    # <MCOperand Reg:19>>
-; M32R6-NEXT:    mfc1 $2, $f0 # <MCInst #1837 MFC1
+; M32R6-NEXT:    mfc1 $2, $f0 # <MCInst #1838 MFC1
 ; M32R6-NEXT:    # <MCOperand Reg:321>
 ; M32R6-NEXT:    # <MCOperand Reg:147>>
 ;
 ; M64-LABEL: test1:
 ; M64:       # %bb.0: # %entry
-; M64-NEXT:    trunc.w.s $f0, $f12 # <MCInst #2637 TRUNC_W_S
+; M64-NEXT:    trunc.w.s $f0, $f12 # <MCInst #2638 TRUNC_W_S
 ; M64-NEXT:    # <MCOperand Reg:147>
 ; M64-NEXT:    # <MCOperand Reg:159>>
-; M64-NEXT:    jr $ra # <MCInst #1628 JR
+; M64-NEXT:    jr $ra # <MCInst #1629 JR
 ; M64-NEXT:    # <MCOperand Reg:301>>
-; M64-NEXT:    mfc1 $2, $f0 # <MCInst #1837 MFC1
+; M64-NEXT:    mfc1 $2, $f0 # <MCInst #1838 MFC1
 ; M64-NEXT:    # <MCOperand Reg:321>
 ; M64-NEXT:    # <MCOperand Reg:147>>
 ;
 ; M64R6-LABEL: test1:
 ; M64R6:       # %bb.0: # %entry
-; M64R6-NEXT:    trunc.w.s $f0, $f12 # <MCInst #2637 TRUNC_W_S
+; M64R6-NEXT:    trunc.w.s $f0, $f12 # <MCInst #2638 TRUNC_W_S
 ; M64R6-NEXT:    # <MCOperand Reg:147>
 ; M64R6-NEXT:    # <MCOperand Reg:159>>
-; M64R6-NEXT:    jr $ra # <MCInst #1609 JALR64
+; M64R6-NEXT:    jr $ra # <MCInst #1610 JALR64
 ; M64R6-NEXT:    # <MCOperand Reg:355>
 ; M64R6-NEXT:    # <MCOperand Reg:301>>
-; M64R6-NEXT:    mfc1 $2, $f0 # <MCInst #1837 MFC1
+; M64R6-NEXT:    mfc1 $2, $f0 # <MCInst #1838 MFC1
 ; M64R6-NEXT:    # <MCOperand Reg:321>
 ; M64R6-NEXT:    # <MCOperand Reg:147>>
 ;
 ; MMR2-FP32-LABEL: test1:
 ; MMR2-FP32:       # %bb.0: # %entry
-; MMR2-FP32-NEXT:    trunc.w.s $f0, $f12 # <MCInst #2638 TRUNC_W_S_MM
+; MMR2-FP32-NEXT:    trunc.w.s $f0, $f12 # <MCInst #2639 TRUNC_W_S_MM
 ; MMR2-FP32-NEXT:    # <MCOperand Reg:147>
 ; MMR2-FP32-NEXT:    # <MCOperand Reg:159>>
-; MMR2-FP32-NEXT:    jr $ra # <MCInst #1639 JR_MM
+; MMR2-FP32-NEXT:    jr $ra # <MCInst #1640 JR_MM
 ; MMR2-FP32-NEXT:    # <MCOperand Reg:19>>
-; MMR2-FP32-NEXT:    mfc1 $2, $f0 # <MCInst #1839 MFC1_MM
+; MMR2-FP32-NEXT:    mfc1 $2, $f0 # <MCInst #1840 MFC1_MM
 ; MMR2-FP32-NEXT:    # <MCOperand Reg:321>
 ; MMR2-FP32-NEXT:    # <MCOperand Reg:147>>
 ;
 ; MMR2-FP64-LABEL: test1:
 ; MMR2-FP64:       # %bb.0: # %entry
-; MMR2-FP64-NEXT:    trunc.w.s $f0, $f12 # <MCInst #2638 TRUNC_W_S_MM
+; MMR2-FP64-NEXT:    trunc.w.s $f0, $f12 # <MCInst #2639 TRUNC_W_S_MM
 ; MMR2-FP64-NEXT:    # <MCOperand Reg:147>
 ; MMR2-FP64-NEXT:    # <MCOperand Reg:159>>
-; MMR2-FP64-NEXT:    jr $ra # <MCInst #1639 JR_MM
+; MMR2-FP64-NEXT:    jr $ra # <MCInst #1640 JR_MM
 ; MMR2-FP64-NEXT:    # <MCOperand Reg:19>>
-; MMR2-FP64-NEXT:    mfc1 $2, $f0 # <MCInst #1839 MFC1_MM
+; MMR2-FP64-NEXT:    mfc1 $2, $f0 # <MCInst #1840 MFC1_MM
 ; MMR2-FP64-NEXT:    # <MCOperand Reg:321>
 ; MMR2-FP64-NEXT:    # <MCOperand Reg:147>>
 ;
@@ -163,36 +163,36 @@
 ; MMR2-SF-NEXT:    # <MCOperand Imm:-24>>
 ; MMR2-SF-NEXT:    .cfi_def_cfa_offset 24
 ; MMR2-SF-NEXT:    sw $ra, 20($sp) # 4-byte Folded Spill
-; MMR2-SF-NEXT:    # <MCInst #2547 SWSP_MM
+; MMR2-SF-NEXT:    # <MCInst #2548 SWSP_MM
 ; MMR2-SF-NEXT:    # <MCOperand Reg:19>
 ; MMR2-SF-NEXT:    # <MCOperand Reg:20>
 ; MMR2-SF-NEXT:    # <MCOperand Imm:20>>
 ; MMR2-SF-NEXT:    .cfi_offset 31, -4
-; MMR2-SF-NEXT:    jal __fixsfsi # <MCInst #1621 JAL_MM
+; MMR2-SF-NEXT:    jal __fixsfsi # <MCInst #1622 JAL_MM
 ; MMR2-SF-NEXT:    # <MCOperand Expr:(__fixsfsi)>>
-; MMR2-SF-NEXT:    nop # <MCInst #2370 SLL
+; MMR2-SF-NEXT:    nop # <MCInst #2371 SLL
 ; MMR2-SF-NEXT:    # <MCOperand Reg:21>
 ; MMR2-SF-NEXT:    # <MCOperand Reg:21>
 ; MMR2-SF-NEXT:    # <MCOperand Imm:0>>
 ; MMR2-SF-NEXT:    lw $ra, 20($sp) # 4-byte Folded Reload
-; MMR2-SF-NEXT:    # <MCInst #1752 LWSP_MM
+; MMR2-SF-NEXT:    # <MCInst #1753 LWSP_MM
 ; MMR2-SF-NEXT:    # <MCOperand Reg:19>
 ; MMR2-SF-NEXT:    # <MCOperand Reg:20>
 ; MMR2-SF-NEXT:    # <MCOperand Imm:20>>
 ; MMR2-SF-NEXT:    addiusp 24 # <MCInst #561 ADDIUSP_MM
 ; MMR2-SF-NEXT:    # <MCOperand Imm:24>>
-; MMR2-SF-NEXT:    jrc $ra # <MCInst #1632 JRC16_MM
+; MMR2-SF-NEXT:    jrc $ra # <MCInst #1633 JRC16_MM
 ; MMR2-SF-NEXT:    # <MCOperand Reg:19>>
 ;
 ; MMR6-LABEL: test1:
 ; MMR6:       # %bb.0: # %entry
-; MMR6-NEXT:    trunc.w.s $f0, $f12 # <MCInst #2639 TRUNC_W_S_MMR6
+; MMR6-NEXT:    trunc.w.s $f0, $f12 # <MCInst #2640 TRUNC_W_S_MMR6
 ; MMR6-NEXT:    # <MCOperand Reg:147>
 ; MMR6-NEXT:    # <MCOperand Reg:159>>
-; MMR6-NEXT:    mfc1 $2, $f0 # <MCInst #1839 MFC1_MM
+; MMR6-NEXT:    mfc1 $2, $f0 # <MCInst #1840 MFC1_MM
 ; MMR6-NEXT:    # <MCOperand Reg:321>
 ; MMR6-NEXT:    # <MCOperand Reg:147>>
-; MMR6-NEXT:    jrc $ra # <MCInst #1632 JRC16_MM
+; MMR6-NEXT:    jrc $ra # <MCInst #1633 JRC16_MM
 ; MMR6-NEXT:    # <MCOperand Reg:19>>
 ;
 ; MMR6-SF-LABEL: test1:
@@ -203,15 +203,15 @@
 ; MMR6-SF-NEXT:    # <MCOperand Imm:-24>>
 ; MMR6-SF-NEXT:    .cfi_def_cfa_offset 24
 ; MMR6-SF-NEXT:    sw $ra, 20($sp) # 4-byte Folded Spill
-; MMR6-SF-NEXT:    # <MCInst #2519 SW
+; MMR6-SF-NEXT:    # <MCInst #2520 SW
 ; MMR6-SF-NEXT:    # <MCOperand Reg:19>
 ; MMR6-SF-NEXT:    # <MCOperand Reg:20>
 ; MMR6-SF-NEXT:    # <MCOperand Imm:20>>
 ; MMR6-SF-NEXT:    .cfi_offset 31, -4
-; MMR6-SF-NEXT:    jalr __fixsfsi # <MCInst #1610 JALRC16_MMR6
+; MMR6-SF-NEXT:    jalr __fixsfsi # <MCInst #1611 JALRC16_MMR6
 ; MMR6-SF-NEXT:    # <MCOperand Expr:(__fixsfsi)>>
 ; MMR6-SF-NEXT:    lw $ra, 20($sp) # 4-byte Folded Reload
-; MMR6-SF-NEXT:    # <MCInst #1722 LW
+; MMR6-SF-NEXT:    # <MCInst #1723 LW
 ; MMR6-SF-NEXT:    # <MCOperand Reg:19>
 ; MMR6-SF-NEXT:    # <MCOperand Reg:20>
 ; MMR6-SF-NEXT:    # <MCOperand Imm:20>>
@@ -219,7 +219,7 @@
 ; MMR6-SF-NEXT:    # <MCOperand Reg:20>
 ; MMR6-SF-NEXT:    # <MCOperand Reg:20>
 ; MMR6-SF-NEXT:    # <MCOperand Imm:24>>
-; MMR6-SF-NEXT:    jrc $ra # <MCInst #1632 JRC16_MM
+; MMR6-SF-NEXT:    jrc $ra # <MCInst #1633 JRC16_MM
 ; MMR6-SF-NEXT:    # <MCOperand Reg:19>>
 entry:
   %conv = fptosi float %t to i32
@@ -229,23 +229,23 @@
 define i32 @test2(double %t) {
 ; M32-LABEL: test2:
 ; M32:       # %bb.0: # %entry
-; M32-NEXT:    trunc.w.d $f0, $f12 # <MCInst #2633 TRUNC_W_D32
+; M32-NEXT:    trunc.w.d $f0, $f12 # <MCInst #2634 TRUNC_W_D32
 ; M32-NEXT:    # <MCOperand Reg:147>
 ; M32-NEXT:    # <MCOperand Reg:133>>
-; M32-NEXT:    jr $ra # <MCInst #1628 JR
+; M32-NEXT:    jr $ra # <MCInst #1629 JR
 ; M32-NEXT:    # <MCOperand Reg:19>>
-; M32-NEXT:    mfc1 $2, $f0 # <MCInst #1837 MFC1
+; M32-NEXT:    mfc1 $2, $f0 # <MCInst #1838 MFC1
 ; M32-NEXT:    # <MCOperand Reg:321>
 ; M32-NEXT:    # <MCOperand Reg:147>>
 ;
 ; M32R2-FP64-LABEL: test2:
 ; M32R2-FP64:       # %bb.0: # %entry
-; M32R2-FP64-NEXT:    trunc.w.d $f0, $f12 # <MCInst #2634 TRUNC_W_D64
+; M32R2-FP64-NEXT:    trunc.w.d $f0, $f12 # <MCInst #2635 TRUNC_W_D64
 ; M32R2-FP64-NEXT:    # <MCOperand Reg:147>
 ; M32R2-FP64-NEXT:    # <MCOperand Reg:373>>
-; M32R2-FP64-NEXT:    jr $ra # <MCInst #1628 JR
+; M32R2-FP64-NEXT:    jr $ra # <MCInst #1629 JR
 ; M32R2-FP64-NEXT:    # <MCOperand Reg:19>>
-; M32R2-FP64-NEXT:    mfc1 $2, $f0 # <MCInst #1837 MFC1
+; M32R2-FP64-NEXT:    mfc1 $2, $f0 # <MCInst #1838 MFC1
 ; M32R2-FP64-NEXT:    # <MCOperand Reg:321>
 ; M32R2-FP64-NEXT:    # <MCOperand Reg:147>>
 ;
@@ -257,23 +257,23 @@
 ; M32R2-SF-NEXT:    # <MCOperand Imm:-24>>
 ; M32R2-SF-NEXT:    .cfi_def_cfa_offset 24
 ; M32R2-SF-NEXT:    sw $ra, 20($sp) # 4-byte Folded Spill
-; M32R2-SF-NEXT:    # <MCInst #2519 SW
+; M32R2-SF-NEXT:    # <MCInst #2520 SW
 ; M32R2-SF-NEXT:    # <MCOperand Reg:19>
 ; M32R2-SF-NEXT:    # <MCOperand Reg:20>
 ; M32R2-SF-NEXT:    # <MCOperand Imm:20>>
 ; M32R2-SF-NEXT:    .cfi_offset 31, -4
-; M32R2-SF-NEXT:    jal __fixdfsi # <MCInst #1606 JAL
+; M32R2-SF-NEXT:    jal __fixdfsi # <MCInst #1607 JAL
 ; M32R2-SF-NEXT:    # <MCOperand Expr:(__fixdfsi)>>
-; M32R2-SF-NEXT:    nop # <MCInst #2370 SLL
+; M32R2-SF-NEXT:    nop # <MCInst #2371 SLL
 ; M32R2-SF-NEXT:    # <MCOperand Reg:21>
 ; M32R2-SF-NEXT:    # <MCOperand Reg:21>
 ; M32R2-SF-NEXT:    # <MCOperand Imm:0>>
 ; M32R2-SF-NEXT:    lw $ra, 20($sp) # 4-byte Folded Reload
-; M32R2-SF-NEXT:    # <MCInst #1722 LW
+; M32R2-SF-NEXT:    # <MCInst #1723 LW
 ; M32R2-SF-NEXT:    # <MCOperand Reg:19>
 ; M32R2-SF-NEXT:    # <MCOperand Reg:20>
 ; M32R2-SF-NEXT:    # <MCOperand Imm:20>>
-; M32R2-SF-NEXT:    jr $ra # <MCInst #1628 JR
+; M32R2-SF-NEXT:    jr $ra # <MCInst #1629 JR
 ; M32R2-SF-NEXT:    # <MCOperand Reg:19>>
 ; M32R2-SF-NEXT:    addiu $sp, $sp, 24 # <MCInst #624 ADDiu
 ; M32R2-SF-NEXT:    # <MCOperand Reg:20>
@@ -282,58 +282,58 @@
 ;
 ; M32R3R5-LABEL: test2:
 ; M32R3R5:       # %bb.0: # %entry
-; M32R3R5-NEXT:    trunc.w.d $f0, $f12 # <MCInst #2633 TRUNC_W_D32
+; M32R3R5-NEXT:    trunc.w.d $f0, $f12 # <MCInst #2634 TRUNC_W_D32
 ; M32R3R5-NEXT:    # <MCOperand Reg:147>
 ; M32R3R5-NEXT:    # <MCOperand Reg:133>>
-; M32R3R5-NEXT:    jr $ra # <MCInst #1628 JR
+; M32R3R5-NEXT:    jr $ra # <MCInst #1629 JR
 ; M32R3R5-NEXT:    # <MCOperand Reg:19>>
-; M32R3R5-NEXT:    mfc1 $2, $f0 # <MCInst #1837 MFC1
+; M32R3R5-NEXT:    mfc1 $2, $f0 # <MCInst #1838 MFC1
 ; M32R3R5-NEXT:    # <MCOperand Reg:321>
 ; M32R3R5-NEXT:    # <MCOperand Reg:147>>
 ;
 ; M32R6-LABEL: test2:
 ; M32R6:       # %bb.0: # %entry
-; M32R6-NEXT:    trunc.w.d $f0, $f12 # <MCInst #2634 TRUNC_W_D64
+; M32R6-NEXT:    trunc.w.d $f0, $f12 # <MCInst #2635 TRUNC_W_D64
 ; M32R6-NEXT:    # <MCOperand Reg:147>
 ; M32R6-NEXT:    # <MCOperand Reg:373>>
-; M32R6-NEXT:    jr $ra # <MCInst #1607 JALR
+; M32R6-NEXT:    jr $ra # <MCInst #1608 JALR
 ; M32R6-NEXT:    # <MCOperand Reg:21>
 ; M32R6-NEXT:    # <MCOperand Reg:19>>
-; M32R6-NEXT:    mfc1 $2, $f0 # <MCInst #1837 MFC1
+; M32R6-NEXT:    mfc1 $2, $f0 # <MCInst #1838 MFC1
 ; M32R6-NEXT:    # <MCOperand Reg:321>
 ; M32R6-NEXT:    # <MCOperand Reg:147>>
 ;
 ; M64-LABEL: test2:
 ; M64:       # %bb.0: # %entry
-; M64-NEXT:    trunc.w.d $f0, $f12 # <MCInst #2634 TRUNC_W_D64
+; M64-NEXT:    trunc.w.d $f0, $f12 # <MCInst #2635 TRUNC_W_D64
 ; M64-NEXT:    # <MCOperand Reg:147>
 ; M64-NEXT:    # <MCOperand Reg:373>>
-; M64-NEXT:    jr $ra # <MCInst #1628 JR
+; M64-NEXT:    jr $ra # <MCInst #1629 JR
 ; M64-NEXT:    # <MCOperand Reg:301>>
-; M64-NEXT:    mfc1 $2, $f0 # <MCInst #1837 MFC1
+; M64-NEXT:    mfc1 $2, $f0 # <MCInst #1838 MFC1
 ; M64-NEXT:    # <MCOperand Reg:321>
 ; M64-NEXT:    # <MCOperand Reg:147>>
 ;
 ; M64R6-LABEL: test2:
 ; M64R6:       # %bb.0: # %entry
-; M64R6-NEXT:    trunc.w.d $f0, $f12 # <MCInst #2634 TRUNC_W_D64
+; M64R6-NEXT:    trunc.w.d $f0, $f12 # <MCInst #2635 TRUNC_W_D64
 ; M64R6-NEXT:    # <MCOperand Reg:147>
 ; M64R6-NEXT:    # <MCOperand Reg:373>>
-; M64R6-NEXT:    jr $ra # <MCInst #1609 JALR64
+; M64R6-NEXT:    jr $ra # <MCInst #1610 JALR64
 ; M64R6-NEXT:    # <MCOperand Reg:355>
 ; M64R6-NEXT:    # <MCOperand Reg:301>>
-; M64R6-NEXT:    mfc1 $2, $f0 # <MCInst #1837 MFC1
+; M64R6-NEXT:    mfc1 $2, $f0 # <MCInst #1838 MFC1
 ; M64R6-NEXT:    # <MCOperand Reg:321>
 ; M64R6-NEXT:    # <MCOperand Reg:147>>
 ;
 ; MMR2-FP32-LABEL: test2:
 ; MMR2-FP32:       # %bb.0: # %entry
-; MMR2-FP32-NEXT:    trunc.w.d $f0, $f12 # <MCInst #2636 TRUNC_W_MM
+; MMR2-FP32-NEXT:    trunc.w.d $f0, $f12 # <MCInst #2637 TRUNC_W_MM
 ; MMR2-FP32-NEXT:    # <MCOperand Reg:147>
 ; MMR2-FP32-NEXT:    # <MCOperand Reg:133>>
-; MMR2-FP32-NEXT:    jr $ra # <MCInst #1639 JR_MM
+; MMR2-FP32-NEXT:    jr $ra # <MCInst #1640 JR_MM
 ; MMR2-FP32-NEXT:    # <MCOperand Reg:19>>
-; MMR2-FP32-NEXT:    mfc1 $2, $f0 # <MCInst #1839 MFC1_MM
+; MMR2-FP32-NEXT:    mfc1 $2, $f0 # <MCInst #1840 MFC1_MM
 ; MMR2-FP32-NEXT:    # <MCOperand Reg:321>
 ; MMR2-FP32-NEXT:    # <MCOperand Reg:147>>
 ;
@@ -342,9 +342,9 @@
 ; MMR2-FP64-NEXT:    cvt.w.d $f0, $f12 # <MCInst #1097 CVT_W_D64_MM
 ; MMR2-FP64-NEXT:    # <MCOperand Reg:147>
 ; MMR2-FP64-NEXT:    # <MCOperand Reg:373>>
-; MMR2-FP64-NEXT:    jr $ra # <MCInst #1639 JR_MM
+; MMR2-FP64-NEXT:    jr $ra # <MCInst #1640 JR_MM
 ; MMR2-FP64-NEXT:    # <MCOperand Reg:19>>
-; MMR2-FP64-NEXT:    mfc1 $2, $f0 # <MCInst #1839 MFC1_MM
+; MMR2-FP64-NEXT:    mfc1 $2, $f0 # <MCInst #1840 MFC1_MM
 ; MMR2-FP64-NEXT:    # <MCOperand Reg:321>
 ; MMR2-FP64-NEXT:    # <MCOperand Reg:147>>
 ;
@@ -354,36 +354,36 @@
 ; MMR2-SF-NEXT:    # <MCOperand Imm:-24>>
 ; MMR2-SF-NEXT:    .cfi_def_cfa_offset 24
 ; MMR2-SF-NEXT:    sw $ra, 20($sp) # 4-byte Folded Spill
-; MMR2-SF-NEXT:    # <MCInst #2547 SWSP_MM
+; MMR2-SF-NEXT:    # <MCInst #2548 SWSP_MM
 ; MMR2-SF-NEXT:    # <MCOperand Reg:19>
 ; MMR2-SF-NEXT:    # <MCOperand Reg:20>
 ; MMR2-SF-NEXT:    # <MCOperand Imm:20>>
 ; MMR2-SF-NEXT:    .cfi_offset 31, -4
-; MMR2-SF-NEXT:    jal __fixdfsi # <MCInst #1621 JAL_MM
+; MMR2-SF-NEXT:    jal __fixdfsi # <MCInst #1622 JAL_MM
 ; MMR2-SF-NEXT:    # <MCOperand Expr:(__fixdfsi)>>
-; MMR2-SF-NEXT:    nop # <MCInst #2370 SLL
+; MMR2-SF-NEXT:    nop # <MCInst #2371 SLL
 ; MMR2-SF-NEXT:    # <MCOperand Reg:21>
 ; MMR2-SF-NEXT:    # <MCOperand Reg:21>
 ; MMR2-SF-NEXT:    # <MCOperand Imm:0>>
 ; MMR2-SF-NEXT:    lw $ra, 20($sp) # 4-byte Folded Reload
-; MMR2-SF-NEXT:    # <MCInst #1752 LWSP_MM
+; MMR2-SF-NEXT:    # <MCInst #1753 LWSP_MM
 ; MMR2-SF-NEXT:    # <MCOperand Reg:19>
 ; MMR2-SF-NEXT:    # <MCOperand Reg:20>
 ; MMR2-SF-NEXT:    # <MCOperand Imm:20>>
 ; MMR2-SF-NEXT:    addiusp 24 # <MCInst #561 ADDIUSP_MM
 ; MMR2-SF-NEXT:    # <MCOperand Imm:24>>
-; MMR2-SF-NEXT:    jrc $ra # <MCInst #1632 JRC16_MM
+; MMR2-SF-NEXT:    jrc $ra # <MCInst #1633 JRC16_MM
 ; MMR2-SF-NEXT:    # <MCOperand Reg:19>>
 ;
 ; MMR6-LABEL: test2:
 ; MMR6:       # %bb.0: # %entry
-; MMR6-NEXT:    trunc.w.d $f0, $f12 # <MCInst #2635 TRUNC_W_D_MMR6
+; MMR6-NEXT:    trunc.w.d $f0, $f12 # <MCInst #2636 TRUNC_W_D_MMR6
 ; MMR6-NEXT:    # <MCOperand Reg:147>
 ; MMR6-NEXT:    # <MCOperand Reg:373>>
-; MMR6-NEXT:    mfc1 $2, $f0 # <MCInst #1839 MFC1_MM
+; MMR6-NEXT:    mfc1 $2, $f0 # <MCInst #1840 MFC1_MM
 ; MMR6-NEXT:    # <MCOperand Reg:321>
 ; MMR6-NEXT:    # <MCOperand Reg:147>>
-; MMR6-NEXT:    jrc $ra # <MCInst #1632 JRC16_MM
+; MMR6-NEXT:    jrc $ra # <MCInst #1633 JRC16_MM
 ; MMR6-NEXT:    # <MCOperand Reg:19>>
 ;
 ; MMR6-SF-LABEL: test2:
@@ -394,15 +394,15 @@
 ; MMR6-SF-NEXT:    # <MCOperand Imm:-24>>
 ; MMR6-SF-NEXT:    .cfi_def_cfa_offset 24
 ; MMR6-SF-NEXT:    sw $ra, 20($sp) # 4-byte Folded Spill
-; MMR6-SF-NEXT:    # <MCInst #2519 SW
+; MMR6-SF-NEXT:    # <MCInst #2520 SW
 ; MMR6-SF-NEXT:    # <MCOperand Reg:19>
 ; MMR6-SF-NEXT:    # <MCOperand Reg:20>
 ; MMR6-SF-NEXT:    # <MCOperand Imm:20>>
 ; MMR6-SF-NEXT:    .cfi_offset 31, -4
-; MMR6-SF-NEXT:    jalr __fixdfsi # <MCInst #1610 JALRC16_MMR6
+; MMR6-SF-NEXT:    jalr __fixdfsi # <MCInst #1611 JALRC16_MMR6
 ; MMR6-SF-NEXT:    # <MCOperand Expr:(__fixdfsi)>>
 ; MMR6-SF-NEXT:    lw $ra, 20($sp) # 4-byte Folded Reload
-; MMR6-SF-NEXT:    # <MCInst #1722 LW
+; MMR6-SF-NEXT:    # <MCInst #1723 LW
 ; MMR6-SF-NEXT:    # <MCOperand Reg:19>
 ; MMR6-SF-NEXT:    # <MCOperand Reg:20>
 ; MMR6-SF-NEXT:    # <MCOperand Imm:20>>
@@ -410,7 +410,7 @@
 ; MMR6-SF-NEXT:    # <MCOperand Reg:20>
 ; MMR6-SF-NEXT:    # <MCOperand Reg:20>
 ; MMR6-SF-NEXT:    # <MCOperand Imm:24>>
-; MMR6-SF-NEXT:    jrc $ra # <MCInst #1632 JRC16_MM
+; MMR6-SF-NEXT:    jrc $ra # <MCInst #1633 JRC16_MM
 ; MMR6-SF-NEXT:    # <MCOperand Reg:19>>
 entry:
   %conv = fptosi double %t to i32
diff --git a/test/CodeGen/Mips/micromips-mtc-mfc.ll b/test/CodeGen/Mips/micromips-mtc-mfc.ll
index c60b006..e23f076 100644
--- a/test/CodeGen/Mips/micromips-mtc-mfc.ll
+++ b/test/CodeGen/Mips/micromips-mtc-mfc.ll
@@ -23,7 +23,7 @@
 ;
 ; MM6-LABEL: foo:
 ; MM6:       # %bb.0: # %entry
-; MM6-NEXT:    mov.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x06]
+; MM6-NEXT:    mov.d $f0, $f12 # encoding: [0x54,0x0c,0x20,0x7b]
 ; MM6-NEXT:    mtc1 $zero, $f1 # encoding: [0x54,0x01,0x28,0x3b]
 ; MM6-NEXT:    mthc1 $zero, $f1 # encoding: [0x54,0x01,0x38,0x3b]
 ; MM6-NEXT:    cmp.ule.d $f1, $f12, $f1 # encoding: [0x54,0x2c,0x09,0xd5]
diff --git a/test/CodeGen/Mips/micromips-pseudo-mtlohi-expand.ll b/test/CodeGen/Mips/micromips-pseudo-mtlohi-expand.ll
index b0b62e8..b63fbb9 100644
--- a/test/CodeGen/Mips/micromips-pseudo-mtlohi-expand.ll
+++ b/test/CodeGen/Mips/micromips-pseudo-mtlohi-expand.ll
@@ -7,51 +7,51 @@
 define i64 @test(i32 signext %a, i32 signext %b) {
 ; MMR2-LABEL: test:
 ; MMR2:       # %bb.0: # %entry
-; MMR2-NEXT:    li16 $2, 0 # <MCInst #1700 LI16_MM
+; MMR2-NEXT:    li16 $2, 0 # <MCInst #1701 LI16_MM
 ; MMR2-NEXT:    # <MCOperand Reg:321>
 ; MMR2-NEXT:    # <MCOperand Imm:0>>
-; MMR2-NEXT:    li16 $3, 1 # <MCInst #1700 LI16_MM
+; MMR2-NEXT:    li16 $3, 1 # <MCInst #1701 LI16_MM
 ; MMR2-NEXT:    # <MCOperand Reg:322>
 ; MMR2-NEXT:    # <MCOperand Imm:1>>
-; MMR2-NEXT:    mtlo $3 # <MCInst #2008 MTLO_MM
+; MMR2-NEXT:    mtlo $3 # <MCInst #2009 MTLO_MM
 ; MMR2-NEXT:    # <MCOperand Reg:322>>
-; MMR2-NEXT:    mthi $2 # <MCInst #2001 MTHI_MM
+; MMR2-NEXT:    mthi $2 # <MCInst #2002 MTHI_MM
 ; MMR2-NEXT:    # <MCOperand Reg:321>>
-; MMR2-NEXT:    madd $4, $5 # <MCInst #1774 MADD
+; MMR2-NEXT:    madd $4, $5 # <MCInst #1775 MADD
 ; MMR2-NEXT:    # <MCOperand Reg:22>
 ; MMR2-NEXT:    # <MCOperand Reg:23>>
-; MMR2-NEXT:    mflo16 $2 # <MCInst #1860 MFLO16_MM
+; MMR2-NEXT:    mflo16 $2 # <MCInst #1861 MFLO16_MM
 ; MMR2-NEXT:    # <MCOperand Reg:321>>
-; MMR2-NEXT:    mfhi16 $3 # <MCInst #1854 MFHI16_MM
+; MMR2-NEXT:    mfhi16 $3 # <MCInst #1855 MFHI16_MM
 ; MMR2-NEXT:    # <MCOperand Reg:322>>
-; MMR2-NEXT:    jrc $ra # <MCInst #1632 JRC16_MM
+; MMR2-NEXT:    jrc $ra # <MCInst #1633 JRC16_MM
 ; MMR2-NEXT:    # <MCOperand Reg:19>>
 ;
 ; MMR2-DSP-LABEL: test:
 ; MMR2-DSP:       # %bb.0: # %entry
-; MMR2-DSP-NEXT:    li16 $2, 0 # <MCInst #1700 LI16_MM
+; MMR2-DSP-NEXT:    li16 $2, 0 # <MCInst #1701 LI16_MM
 ; MMR2-DSP-NEXT:    # <MCOperand Reg:321>
 ; MMR2-DSP-NEXT:    # <MCOperand Imm:0>>
-; MMR2-DSP-NEXT:    li16 $3, 1 # <MCInst #1700 LI16_MM
+; MMR2-DSP-NEXT:    li16 $3, 1 # <MCInst #1701 LI16_MM
 ; MMR2-DSP-NEXT:    # <MCOperand Reg:322>
 ; MMR2-DSP-NEXT:    # <MCOperand Imm:1>>
-; MMR2-DSP-NEXT:    mtlo $3, $ac0 # <MCInst #2006 MTLO_DSP
+; MMR2-DSP-NEXT:    mtlo $3, $ac0 # <MCInst #2007 MTLO_DSP
 ; MMR2-DSP-NEXT:    # <MCOperand Reg:291>
 ; MMR2-DSP-NEXT:    # <MCOperand Reg:322>>
-; MMR2-DSP-NEXT:    mthi $2, $ac0 # <MCInst #1999 MTHI_DSP
+; MMR2-DSP-NEXT:    mthi $2, $ac0 # <MCInst #2000 MTHI_DSP
 ; MMR2-DSP-NEXT:    # <MCOperand Reg:253>
 ; MMR2-DSP-NEXT:    # <MCOperand Reg:321>>
-; MMR2-DSP-NEXT:    madd $ac0, $4, $5 # <MCInst #1792 MADD_DSP
+; MMR2-DSP-NEXT:    madd $ac0, $4, $5 # <MCInst #1793 MADD_DSP
 ; MMR2-DSP-NEXT:    # <MCOperand Reg:26>
 ; MMR2-DSP-NEXT:    # <MCOperand Reg:22>
 ; MMR2-DSP-NEXT:    # <MCOperand Reg:23>
 ; MMR2-DSP-NEXT:    # <MCOperand Reg:26>>
-; MMR2-DSP-NEXT:    mflo $2, $ac0 # <MCInst #1862 MFLO_DSP
+; MMR2-DSP-NEXT:    mflo $2, $ac0 # <MCInst #1863 MFLO_DSP
 ; MMR2-DSP-NEXT:    # <MCOperand Reg:321>
 ; MMR2-DSP-NEXT:    # <MCOperand Reg:26>>
-; MMR2-DSP-NEXT:    jr $ra # <MCInst #1639 JR_MM
+; MMR2-DSP-NEXT:    jr $ra # <MCInst #1640 JR_MM
 ; MMR2-DSP-NEXT:    # <MCOperand Reg:19>>
-; MMR2-DSP-NEXT:    mfhi $3, $ac0 # <MCInst #1856 MFHI_DSP
+; MMR2-DSP-NEXT:    mfhi $3, $ac0 # <MCInst #1857 MFHI_DSP
 ; MMR2-DSP-NEXT:    # <MCOperand Reg:322>
 ; MMR2-DSP-NEXT:    # <MCOperand Reg:26>>
 entry: