commit a5912ea9c6989fe2da9f6fead08dd228b8f74e81
author Tim Renouf <tpr.llvm@botech.co.uk> Mon Apr 15 10:36:24 2019 +0000
committer Tim Renouf <tpr.llvm@botech.co.uk> Mon Apr 15 10:36:24 2019 +0000
tree 4882f1f97702d2f0b1cabb9731030d26210c0f49
parent 6ce3cbed7bf7cb0e98961b1ce9aa2c53250090cf

[AMDGPU] Fixed incorrect test in vcnd/vcmp optimization

This fixes a test I introduced in change D59191 (that added src0 and
src1 modifiers to the v_cndmask instruction for disassembly purposes).

Spotted by David Binderman in bug 41488.

Differential Revision: https://reviews.llvm.org/D60652

Change-Id: I6ac95e66cd84e812ed3359ad57bcd0e13198ba0c

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358392 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp

diff --git a/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp b/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp
index 9db1e5a..7e843e8 100644
--- a/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp
+++ b/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp
@@ -223,7 +223,7 @@
     return AMDGPU::NoRegister;
 
   if (TII->hasModifiersSet(*Sel, AMDGPU::OpName::src0_modifiers) ||
-      TII->hasModifiersSet(*Sel, AMDGPU::OpName::src0_modifiers))
+      TII->hasModifiersSet(*Sel, AMDGPU::OpName::src1_modifiers))
     return AMDGPU::NoRegister;
 
   Op1 = TII->getNamedOperand(*Sel, AMDGPU::OpName::src0);