tree 734fec768e4b05259d235a00bbd233f1fc960597
parent a8f354662a73aeb5425ca6b5351cbe3c5dbfa390
author Diana Picus <diana.picus@linaro.org> 1553504069 +0000
committer Diana Picus <diana.picus@linaro.org> 1553504069 +0000

[ARM GlobalISel] 64-bit memops should be aligned

We currently use only VLDR/VSTR for all 64-bit loads/stores, so the
memory operands must be word-aligned. Mark aligned operations as legal
and narrow non-aligned ones to 32 bits.

While we're here, also mark non-power-of-2 loads/stores as unsupported.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356872 91177308-0d34-0410-b5e6-96231b3b80d8