tree 900fa8d881cadf37b2dceb8f77a565eefc0ae36b
parent 4d12ab485a42dfb7315be497f4295f948866d0ff
author Tim Renouf <tpr.llvm@botech.co.uk> 1553169681 +0000
committer Tim Renouf <tpr.llvm@botech.co.uk> 1553169681 +0000

[AMDGPU] Support for v3i32/v3f32

Added support for dwordx3 for most load/store types, but not DS, and not
intrinsics yet.

SI (gfx6) does not have dwordx3 instructions, so they are not enabled
there.

Some of this patch is from Matt Arsenault, also of AMD.

Differential Revision: https://reviews.llvm.org/D58902

Change-Id: I913ef54f1433a7149da8d72f4af54dbb13436bd9

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356659 91177308-0d34-0410-b5e6-96231b3b80d8