test/CodeGen/X86/sse2-intrinsics-x86_64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mattr=-avx,+sse2 -show-mc-encoding | FileCheck %s --check-prefixes=CHECK,SSE
; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mattr=+avx -show-mc-encoding | FileCheck %s --check-prefixes=CHECK,AVX,AVX1
; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mattr=+avx512f,+avx512bw,+avx512dq,+avx512vl -show-mc-encoding | FileCheck %s --check-prefixes=CHECK,AVX,AVX512

define i64 @test_x86_sse2_cvtsd2si64(<2 x double> %a0) {
; SSE-LABEL: test_x86_sse2_cvtsd2si64:
; SSE:       ## %bb.0:
; SSE-NEXT:    cvtsd2si %xmm0, %rax ## encoding: [0xf2,0x48,0x0f,0x2d,0xc0]
; SSE-NEXT:    retq ## encoding: [0xc3]
;
; AVX1-LABEL: test_x86_sse2_cvtsd2si64:
; AVX1:       ## %bb.0:
; AVX1-NEXT:    vcvtsd2si %xmm0, %rax ## encoding: [0xc4,0xe1,0xfb,0x2d,0xc0]
; AVX1-NEXT:    retq ## encoding: [0xc3]
;
; AVX512-LABEL: test_x86_sse2_cvtsd2si64:
; AVX512:       ## %bb.0:
; AVX512-NEXT:    vcvtsd2si %xmm0, %rax ## EVEX TO VEX Compression encoding: [0xc4,0xe1,0xfb,0x2d,0xc0]
; AVX512-NEXT:    retq ## encoding: [0xc3]
  %res = call i64 @llvm.x86.sse2.cvtsd2si64(<2 x double> %a0) ; <i64> [#uses=1]
  ret i64 %res
}
declare i64 @llvm.x86.sse2.cvtsd2si64(<2 x double>) nounwind readnone


define i64 @test_x86_sse2_cvttsd2si64(<2 x double> %a0) {
; SSE-LABEL: test_x86_sse2_cvttsd2si64:
; SSE:       ## %bb.0:
; SSE-NEXT:    cvttsd2si %xmm0, %rax ## encoding: [0xf2,0x48,0x0f,0x2c,0xc0]
; SSE-NEXT:    retq ## encoding: [0xc3]
;
; AVX1-LABEL: test_x86_sse2_cvttsd2si64:
; AVX1:       ## %bb.0:
; AVX1-NEXT:    vcvttsd2si %xmm0, %rax ## encoding: [0xc4,0xe1,0xfb,0x2c,0xc0]
; AVX1-NEXT:    retq ## encoding: [0xc3]
;
; AVX512-LABEL: test_x86_sse2_cvttsd2si64:
; AVX512:       ## %bb.0:
; AVX512-NEXT:    vcvttsd2si %xmm0, %rax ## EVEX TO VEX Compression encoding: [0xc4,0xe1,0xfb,0x2c,0xc0]
; AVX512-NEXT:    retq ## encoding: [0xc3]
  %res = call i64 @llvm.x86.sse2.cvttsd2si64(<2 x double> %a0) ; <i64> [#uses=1]
  ret i64 %res
}
declare i64 @llvm.x86.sse2.cvttsd2si64(<2 x double>) nounwind readnone