# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
---
name:            shl_v2i32
alignment:       2
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $d0, $d1

    ; CHECK-LABEL: name: shl_v2i32
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
    ; CHECK: [[USHLv2i32_:%[0-9]+]]:fpr64 = USHLv2i32 [[COPY]], [[COPY1]]
    ; CHECK: $d0 = COPY [[USHLv2i32_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %0:fpr(<2 x s32>) = COPY $d0
    %1:fpr(<2 x s32>) = COPY $d1
    %2:fpr(<2 x s32>) = G_SHL %0, %1(<2 x s32>)
    $d0 = COPY %2(<2 x s32>)
    RET_ReallyLR implicit $d0

...
---
name:            shl_v4i32
alignment:       2
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $q0, $q1

    ; CHECK-LABEL: name: shl_v4i32
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
    ; CHECK: [[USHLv4i32_:%[0-9]+]]:fpr128 = USHLv4i32 [[COPY]], [[COPY1]]
    ; CHECK: $q0 = COPY [[USHLv4i32_]]
    ; CHECK: RET_ReallyLR implicit $q0
    %0:fpr(<4 x s32>) = COPY $q0
    %1:fpr(<4 x s32>) = COPY $q1
    %2:fpr(<4 x s32>) = G_SHL %0, %1(<4 x s32>)
    $q0 = COPY %2(<4 x s32>)
    RET_ReallyLR implicit $q0

...
---
name:            ashr_v2i32
alignment:       2
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $d0, $d1

    ; CHECK-LABEL: name: ashr_v2i32
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
    ; CHECK: [[NEGv2i32_:%[0-9]+]]:fpr64 = NEGv2i32 [[COPY1]]
    ; CHECK: [[SSHLv2i32_:%[0-9]+]]:fpr64 = SSHLv2i32 [[COPY]], [[NEGv2i32_]]
    ; CHECK: $d0 = COPY [[SSHLv2i32_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %0:fpr(<2 x s32>) = COPY $d0
    %1:fpr(<2 x s32>) = COPY $d1
    %2:fpr(<2 x s32>) = G_ASHR %0, %1(<2 x s32>)
    $d0 = COPY %2(<2 x s32>)
    RET_ReallyLR implicit $d0

...
---
name:            ashr_v4i32
alignment:       2
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $q0, $q1

    ; CHECK-LABEL: name: ashr_v4i32
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
    ; CHECK: [[NEGv4i32_:%[0-9]+]]:fpr128 = NEGv4i32 [[COPY1]]
    ; CHECK: [[SSHLv4i32_:%[0-9]+]]:fpr128 = SSHLv4i32 [[COPY]], [[NEGv4i32_]]
    ; CHECK: $q0 = COPY [[SSHLv4i32_]]
    ; CHECK: RET_ReallyLR implicit $q0
    %0:fpr(<4 x s32>) = COPY $q0
    %1:fpr(<4 x s32>) = COPY $q1
    %2:fpr(<4 x s32>) = G_ASHR %0, %1(<4 x s32>)
    $q0 = COPY %2(<4 x s32>)
    RET_ReallyLR implicit $q0

...