test/CodeGen/AMDGPU/insert-skips-flat-vmem.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=polaris10 -run-pass si-insert-skips -amdgpu-skip-threshold=1 -verify-machineinstrs  %s -o - | FileCheck %s

---

name: skip_execz_flat
body: |
  ; CHECK-LABEL: name: skip_execz_flat
  ; CHECK: bb.0:
  ; CHECK:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
  ; CHECK:   SI_MASK_BRANCH %bb.2, implicit $exec
  ; CHECK:   S_CBRANCH_EXECZ %bb.2, implicit $exec
  ; CHECK: bb.1:
  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   $vgpr0 = V_MOV_B32_e32 0, implicit $exec
  ; CHECK:   FLAT_STORE_DWORD undef $vgpr1_vgpr2, $vgpr0, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
  ; CHECK: bb.2:
  ; CHECK:   S_ENDPGM 0
  bb.0:
    successors: %bb.1, %bb.2
    SI_MASK_BRANCH %bb.2, implicit $exec

  bb.1:
    successors: %bb.2
    $vgpr0 = V_MOV_B32_e32 0, implicit $exec
    FLAT_STORE_DWORD undef $vgpr1_vgpr2, $vgpr0, 0, 0, 0, 0, implicit $exec, implicit $flat_scr

  bb.2:
    S_ENDPGM 0
...

---

name: skip_execz_mubuf
body: |
  ; CHECK-LABEL: name: skip_execz_mubuf
  ; CHECK: bb.0:
  ; CHECK:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
  ; CHECK:   SI_MASK_BRANCH %bb.2, implicit $exec
  ; CHECK:   S_CBRANCH_EXECZ %bb.2, implicit $exec
  ; CHECK: bb.1:
  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   $vgpr0 = V_MOV_B32_e32 0, implicit $exec
  ; CHECK:   BUFFER_STORE_DWORD_OFFSET $vgpr0, undef $sgpr0_sgpr1_sgpr2_sgpr3, undef $sgpr4, 0, 0, 0, 0, 0, 0, implicit $exec
  ; CHECK: bb.2:
  ; CHECK:   S_ENDPGM 0
  bb.0:
    successors: %bb.1, %bb.2
    SI_MASK_BRANCH %bb.2, implicit $exec

  bb.1:
    successors: %bb.2
    $vgpr0 = V_MOV_B32_e32 0, implicit $exec
    BUFFER_STORE_DWORD_OFFSET $vgpr0, undef $sgpr0_sgpr1_sgpr2_sgpr3, undef $sgpr4, 0, 0, 0, 0, 0, 0, implicit $exec

  bb.2:
    S_ENDPGM 0
...