test/CodeGen/AMDGPU/GlobalISel/regbankselect-sitofp.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s

---
name: sitofp_s
legalized: true

body: |
  bb.0:
    liveins: $sgpr0
    ; CHECK-LABEL: name: sitofp_s
    ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
    ; CHECK: [[SITOFP:%[0-9]+]]:vgpr(s32) = G_SITOFP [[COPY]](s32)
    %0:_(s32) = COPY $sgpr0
    %1:_(s32) = G_SITOFP %0
...

---
name: sitofp_v
legalized: true

body: |
  bb.0:
    liveins: $vgpr0
    ; CHECK-LABEL: name: sitofp_v
    ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
    ; CHECK: [[SITOFP:%[0-9]+]]:vgpr(s32) = G_SITOFP [[COPY]](s32)
    %0:_(s32) = COPY $vgpr0
    %1:_(s32) = G_SITOFP %0
...

---
name: sitofp_s_s1
legalized: true

body: |
  bb.0:
    liveins: $sgpr0
    ; CHECK-LABEL: name: sitofp_s_s1
    ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
    ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
    ; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
    ; CHECK: [[SITOFP:%[0-9]+]]:vgpr(s32) = G_SITOFP [[ICMP]](s1)
    %0:_(s32) = COPY $sgpr0
    %1:_(s32) = G_CONSTANT i32 0
    %2:_(s1) = G_ICMP intpred(eq), %0, %1
    %3:_(s32) = G_SITOFP %2
...

---
name: sitofp_v_s1
legalized: true

body: |
  bb.0:
    liveins: $vgpr0
    ; CHECK-LABEL: name: sitofp_v_s1
    ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
    ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
    ; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
    ; CHECK: [[SITOFP:%[0-9]+]]:vgpr(s32) = G_SITOFP [[ICMP]](s1)
    %0:_(s32) = COPY $vgpr0
    %1:_(s32) = G_CONSTANT i32 0
    %2:_(s1) = G_ICMP intpred(eq), %0, %1
    %3:_(s32) = G_SITOFP %2
...