# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o -  %s| FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o -  %s| FileCheck %s

---
name: kill_scc
legalized: true

body: |
  bb.0:
    liveins: $sgpr0, $sgpr1
    ; CHECK-LABEL: name: kill_scc
    ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
    ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
    ; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
    ; CHECK: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1)
    ; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.kill), [[COPY2]](s1)
    %0:_(s32) = COPY $sgpr0
    %1:_(s32) = COPY $sgpr1
    %2:_(s1) = G_ICMP intpred(eq), %0, %1
    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.kill), %2
...

---
name: kill_vcc
legalized: true

body: |
  bb.0:
    liveins: $vgpr0, $vgpr1
    ; CHECK-LABEL: name: kill_vcc
    ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
    ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
    ; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
    ; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.kill), [[ICMP]](s1)
    %0:_(s32) = COPY $vgpr0
    %1:_(s32) = COPY $vgpr1
    %2:_(s1) = G_ICMP intpred(eq), %0, %1
    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.kill), %2
...

---
name: kill_constant_true
legalized: true

body: |
  bb.0:
    ; CHECK-LABEL: name: kill_constant_true
    ; CHECK: [[C:%[0-9]+]]:sgpr(s1) = G_CONSTANT i1 true
    ; CHECK: [[COPY:%[0-9]+]]:vcc(s1) = COPY [[C]](s1)
    ; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.kill), [[COPY]](s1)
    %0:_(s1) = G_CONSTANT i1 true
    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.kill), %0
...

---
name: kill_constant_false
legalized: true

body: |
  bb.0:
    ; CHECK-LABEL: name: kill_constant_false
    ; CHECK: [[C:%[0-9]+]]:sgpr(s1) = G_CONSTANT i1 false
    ; CHECK: [[COPY:%[0-9]+]]:vcc(s1) = COPY [[C]](s1)
    ; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.kill), [[COPY]](s1)
    %0:_(s1) = G_CONSTANT i1 false
    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.kill), %0
...