| # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py |
| # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s |
| # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s |
| |
| --- |
| name: class_ss |
| legalized: true |
| |
| body: | |
| bb.0: |
| liveins: $sgpr0_sgpr1, $sgpr2 |
| ; CHECK-LABEL: name: class_ss |
| ; CHECK: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1 |
| ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 |
| ; CHECK: [[INT:%[0-9]+]]:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), [[COPY]](s64), [[COPY1]](s32) |
| %0:_(s64) = COPY $sgpr0_sgpr1 |
| %1:_(s32) = COPY $sgpr2 |
| %2:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1 |
| ... |
| |
| --- |
| name: class_sv |
| legalized: true |
| |
| body: | |
| bb.0: |
| liveins: $sgpr0_sgpr1, $vgpr0 |
| |
| ; CHECK-LABEL: name: class_sv |
| ; CHECK: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1 |
| ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 |
| ; CHECK: [[INT:%[0-9]+]]:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), [[COPY]](s64), [[COPY1]](s32) |
| %0:_(s64) = COPY $sgpr0_sgpr1 |
| %1:_(s32) = COPY $vgpr0 |
| %2:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1 |
| ... |
| |
| --- |
| name: class_vs |
| legalized: true |
| |
| body: | |
| bb.0: |
| liveins: $vgpr0_vgpr1, $sgpr0 |
| ; CHECK-LABEL: name: class_vs |
| ; CHECK: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1 |
| ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 |
| ; CHECK: [[INT:%[0-9]+]]:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), [[COPY]](s64), [[COPY1]](s32) |
| %0:_(s64) = COPY $vgpr0_vgpr1 |
| %1:_(s32) = COPY $sgpr0 |
| %2:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1 |
| ... |
| |
| --- |
| name: class_vv |
| legalized: true |
| |
| body: | |
| bb.0: |
| liveins: $vgpr0, $vgpr1 |
| ; CHECK-LABEL: name: class_vv |
| ; CHECK: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1 |
| ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr2 |
| ; CHECK: [[INT:%[0-9]+]]:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), [[COPY]](s64), [[COPY1]](s32) |
| %0:_(s64) = COPY $vgpr0_vgpr1 |
| %1:_(s32) = COPY $vgpr2 |
| %2:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1 |
| ... |