test/CodeGen/AMDGPU/GlobalISel/legalize-fpow.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - | FileCheck %s

---
name: test_fpow_s32
body: |
  bb.0:
    liveins: $vgpr0, $vgpr1

    ; CHECK-LABEL: name: test_fpow_s32
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
    ; CHECK: [[FPOW:%[0-9]+]]:_(s32) = G_FPOW [[COPY]], [[COPY1]]
    ; CHECK: $vgpr0 = COPY [[FPOW]](s32)
    %0:_(s32) = COPY $vgpr0
    %1:_(s32) = COPY $vgpr1
    %2:_(s32) = G_FPOW %0, %1
    $vgpr0 = COPY %2
...

---
name: test_fpow_v2s32
body: |
  bb.0.entry:
    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3

    ; CHECK-LABEL: name: test_fpow_v2s32
    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
    ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
    ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
    ; CHECK: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
    ; CHECK: [[FPOW:%[0-9]+]]:_(s32) = G_FPOW [[UV]], [[UV2]]
    ; CHECK: [[FPOW1:%[0-9]+]]:_(s32) = G_FPOW [[UV1]], [[UV3]]
    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FPOW]](s32), [[FPOW1]](s32)
    ; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
    %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
    %1:_(<2 x s32>) = COPY $vgpr2_vgpr3
    %2:_(<2 x s32>) = G_FPOW %0, %1
    $vgpr0_vgpr1 = COPY %2
...

---
name: test_fpow_v3s32
body: |
  bb.0.entry:
    liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5

    ; CHECK-LABEL: name: test_fpow_v3s32
    ; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
    ; CHECK: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
    ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
    ; CHECK: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
    ; CHECK: [[FPOW:%[0-9]+]]:_(s32) = G_FPOW [[UV]], [[UV3]]
    ; CHECK: [[FPOW1:%[0-9]+]]:_(s32) = G_FPOW [[UV1]], [[UV4]]
    ; CHECK: [[FPOW2:%[0-9]+]]:_(s32) = G_FPOW [[UV2]], [[UV5]]
    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[FPOW]](s32), [[FPOW1]](s32), [[FPOW2]](s32)
    ; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
    %0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
    %1:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
    %2:_(<3 x s32>) = G_FPOW %0, %1
    $vgpr0_vgpr1_vgpr2 = COPY %2
...