test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck %s

---
name: extract_vector_elt_0_v2i32

body: |
  bb.0:
    liveins: $vgpr0_vgpr1
    ; CHECK-LABEL: name: extract_vector_elt_0_v2i32
    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
    ; CHECK: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY]](<2 x s32>), 0
    ; CHECK: $vgpr0 = COPY [[EXTRACT]](s32)
    %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
    %1:_(s32) = G_CONSTANT i32 0
    %2:_(s32) = G_EXTRACT_VECTOR_ELT %0, %1
    $vgpr0 = COPY %2
...
---
name: extract_vector_elt_1_v2i32

body: |
  bb.0:
    liveins: $vgpr0_vgpr1
    ; CHECK-LABEL: name: extract_vector_elt_1_v2i32
    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
    ; CHECK: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY]](<2 x s32>), 32
    ; CHECK: $vgpr0 = COPY [[EXTRACT]](s32)
    %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
    %1:_(s32) = G_CONSTANT i32 1
    %2:_(s32) = G_EXTRACT_VECTOR_ELT %0, %1
    $vgpr0 = COPY %2
...
---
name: extract_vector_elt_2_v2i32

body: |
  bb.0:
    liveins: $vgpr0_vgpr1
    ; CHECK-LABEL: name: extract_vector_elt_2_v2i32
    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
    ; CHECK: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY]](<2 x s32>), 32
    ; CHECK: $vgpr0 = COPY [[EXTRACT]](s32)
    %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
    %1:_(s32) = G_CONSTANT i32 1
    %2:_(s32) = G_EXTRACT_VECTOR_ELT %0, %1
    $vgpr0 = COPY %2
...
---
name: extract_vector_elt_0_v3i32

body: |
  bb.0:
    liveins: $vgpr0_vgpr1_vgpr2
    ; CHECK-LABEL: name: extract_vector_elt_0_v3i32
    ; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
    ; CHECK: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY]](<3 x s32>), 0
    ; CHECK: $vgpr0 = COPY [[EXTRACT]](s32)
    %0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
    %1:_(s32) = G_CONSTANT i32 0
    %2:_(s32) = G_EXTRACT_VECTOR_ELT %0, %1
    $vgpr0 = COPY %2
...
---
name: extract_vector_elt_0_v4i32

body: |
  bb.0:
    liveins: $vgpr0_vgpr1_vgpr2_vgpr3
    ; CHECK-LABEL: name: extract_vector_elt_0_v4i32
    ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
    ; CHECK: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY]](<4 x s32>), 0
    ; CHECK: $vgpr0 = COPY [[EXTRACT]](s32)
    %0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
    %1:_(s32) = G_CONSTANT i32 0
    %2:_(s32) = G_EXTRACT_VECTOR_ELT %0, %1
    $vgpr0 = COPY %2
...

---
name: extract_vector_elt_0_v5i32

body: |
  bb.0:
    liveins: $vgpr0
    ; CHECK-LABEL: name: extract_vector_elt_0_v5i32
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
    ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
    %0:_(s32) = COPY $vgpr0
    %1:_(<5 x s32>) = G_BUILD_VECTOR %0, %0, %0, %0, %0
    %2:_(s32) = G_CONSTANT i32 0
    %3:_(s32) = G_EXTRACT_VECTOR_ELT %1, %2
    $vgpr0 = COPY %3
...

---
name: extract_vector_elt_0_v6i32

body: |
  bb.0:
    liveins: $vgpr0
    ; CHECK-LABEL: name: extract_vector_elt_0_v6i32
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
    ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
    %0:_(s32) = COPY $vgpr0
    %1:_(<6 x s32>) = G_BUILD_VECTOR %0, %0, %0, %0, %0, %0
    %2:_(s32) = G_CONSTANT i32 0
    %3:_(s32) = G_EXTRACT_VECTOR_ELT %1, %2
    $vgpr0 = COPY %3
...

---
name: extract_vector_elt_0_v7i32

body: |
  bb.0:
    liveins: $vgpr0
    ; CHECK-LABEL: name: extract_vector_elt_0_v7i32
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
    ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
    %0:_(s32) = COPY $vgpr0
    %1:_(<7 x s32>) = G_BUILD_VECTOR %0, %0, %0, %0, %0, %0, %0
    %2:_(s32) = G_CONSTANT i32 0
    %3:_(s32) = G_EXTRACT_VECTOR_ELT %1, %2
    $vgpr0 = COPY %3
...

---
name: extract_vector_elt_0_v8i32

body: |
  bb.0:
    liveins: $vgpr0
    ; CHECK-LABEL: name: extract_vector_elt_0_v8i32
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
    ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
    %0:_(s32) = COPY $vgpr0
    %1:_(<8 x s32>) = G_BUILD_VECTOR %0, %0, %0, %0, %0, %0, %0, %0
    %2:_(s32) = G_CONSTANT i32 0
    %3:_(s32) = G_EXTRACT_VECTOR_ELT %1, %2
    $vgpr0 = COPY %3
...

---
name: extract_vector_elt_0_v16i32

body: |
  bb.0:
    liveins: $vgpr0
    ; CHECK-LABEL: name: extract_vector_elt_0_v16i32
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
    ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
    %0:_(s32) = COPY $vgpr0
    %1:_(<16 x s32>) = G_BUILD_VECTOR %0, %0, %0, %0, %0, %0, %0, %0, %0, %0, %0, %0, %0, %0, %0, %0
    %2:_(s32) = G_CONSTANT i32 0
    %3:_(s32) = G_EXTRACT_VECTOR_ELT %1, %2
    $vgpr0 = COPY %3
...

---
name: extract_vector_elt_var_v2i32

body: |
  bb.0:
    liveins: $vgpr0_vgpr1, $vgpr2
    ; CHECK-LABEL: name: extract_vector_elt_var_v2i32
    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
    ; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x s32>), [[COPY1]](s32)
    ; CHECK: $vgpr0 = COPY [[EVEC]](s32)
    %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
    %1:_(s32) = COPY $vgpr2
    %2:_(s32) = G_EXTRACT_VECTOR_ELT %0, %1
    $vgpr0 = COPY %2
...

---
name: extract_vector_elt_var_v8i32

body: |
  bb.0:
    liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
    ; CHECK-LABEL: name: extract_vector_elt_var_v8i32
    ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
    ; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<8 x s32>), [[COPY1]](s32)
    ; CHECK: $vgpr0 = COPY [[EVEC]](s32)
    %0:_(<8 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
    %1:_(s32) = COPY $vgpr2
    %2:_(s32) = G_EXTRACT_VECTOR_ELT %0, %1
    $vgpr0 = COPY %2
...


---
name: extract_vector_elt_0_v2i8_i32

body: |
  bb.0:

    ; CHECK-LABEL: name: extract_vector_elt_0_v2i8_i32
    ; CHECK: [[DEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY [[DEF]](<2 x s32>)
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
    ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
    ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[UV]], [[C]](s32)
    ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[UV1]], [[C]](s32)
    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
    ; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ASHR]](s32), [[ASHR1]](s32)
    ; CHECK: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[BUILD_VECTOR]](<2 x s32>), 0
    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[EXTRACT]](s32)
    ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
    %0:_(<2 x s8>) = G_IMPLICIT_DEF
    %1:_(s32) = G_CONSTANT i32 0
    %2:_(s8) = G_EXTRACT_VECTOR_ELT %0, %1
    %3:_(s32) = G_ANYEXT %2
    $vgpr0 = COPY %3
...

---
name: extract_vector_elt_0_v2i16_i32

body: |
  bb.0:

    ; CHECK-LABEL: name: extract_vector_elt_0_v2i16_i32
    ; CHECK: [[DEF:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
    ; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[DEF]](<2 x s16>)
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
    ; CHECK: $vgpr0 = COPY [[COPY]](s32)
    %0:_(<2 x s16>) = G_IMPLICIT_DEF
    %1:_(s32) = G_CONSTANT i32 0
    %2:_(s16) = G_EXTRACT_VECTOR_ELT %0, %1
    %3:_(s32) = G_ANYEXT %2
    $vgpr0 = COPY %3
...

---
name: extract_vector_elt_0_v2i1_i32

body: |
  bb.0:

    ; CHECK-LABEL: name: extract_vector_elt_0_v2i1_i32
    ; CHECK: [[DEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY [[DEF]](<2 x s32>)
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
    ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
    ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[UV]], [[C]](s32)
    ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[UV1]], [[C]](s32)
    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
    ; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ASHR]](s32), [[ASHR1]](s32)
    ; CHECK: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[BUILD_VECTOR]](<2 x s32>), 0
    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[EXTRACT]](s32)
    ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
    %0:_(<2 x s1>) = G_IMPLICIT_DEF
    %1:_(s32) = G_CONSTANT i32 0
    %2:_(s1) = G_EXTRACT_VECTOR_ELT %0, %1
    %3:_(s32) = G_ANYEXT %2
    $vgpr0 = COPY %3
...

---
name: extract_vector_elt_0_v2i1_i1

body: |
  bb.0:

    ; CHECK-LABEL: name: extract_vector_elt_0_v2i1_i1
    ; CHECK: [[DEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
    ; CHECK: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY [[DEF]](<2 x s32>)
    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
    ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
    ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[UV]], [[C1]](s32)
    ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[UV1]], [[C1]](s32)
    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
    ; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C1]](s32)
    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ASHR]](s32), [[ASHR1]](s32)
    ; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[C]](s1)
    ; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<2 x s32>), [[SEXT]](s32)
    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[EVEC]](s32)
    ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
    %0:_(<2 x s1>) = G_IMPLICIT_DEF
    %1:_(s1) = G_CONSTANT i1 false
    %2:_(s1) = G_EXTRACT_VECTOR_ELT %0, %1
    %3:_(s32) = G_ANYEXT %2
    $vgpr0 = COPY %3
...

---
name: extract_vector_elt_v2s8_varidx_i32

body: |
  bb.0:
    liveins: $vgpr0_vgpr1, $vgpr2

    ; CHECK-LABEL: name: extract_vector_elt_v2s8_varidx_i32
    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
    ; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY [[COPY]](<2 x s32>)
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
    ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<2 x s32>)
    ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[UV]], [[C]](s32)
    ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[UV1]], [[C]](s32)
    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
    ; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ASHR]](s32), [[ASHR1]](s32)
    ; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<2 x s32>), [[COPY1]](s32)
    ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[EVEC]](s32)
    ; CHECK: $vgpr0 = COPY [[COPY3]](s32)
    %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
    %1:_(s32) = COPY $vgpr2
    %2:_(<2 x s8>) = G_TRUNC %0
    %3:_(s8) = G_EXTRACT_VECTOR_ELT %2, %1
    %4:_(s32) = G_ANYEXT %3
    $vgpr0 = COPY %4
...

---
name: extract_vector_elt_v3s8_varidx_i32

body: |
  bb.0:
    liveins: $vgpr0_vgpr1_vgpr2, $vgpr3

    ; CHECK-LABEL: name: extract_vector_elt_v3s8_varidx_i32
    ; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr3
    ; CHECK: [[COPY2:%[0-9]+]]:_(<3 x s32>) = COPY [[COPY]](<3 x s32>)
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
    ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<3 x s32>)
    ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[UV]], [[C]](s32)
    ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[UV1]], [[C]](s32)
    ; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[UV2]], [[C]](s32)
    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
    ; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
    ; CHECK: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32)
    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[ASHR]](s32), [[ASHR1]](s32), [[ASHR2]](s32)
    ; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<3 x s32>), [[COPY1]](s32)
    ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[EVEC]](s32)
    ; CHECK: $vgpr0 = COPY [[COPY3]](s32)
    %0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
    %1:_(s32) = COPY $vgpr3
    %2:_(<3 x s8>) = G_TRUNC %0
    %3:_(s8) = G_EXTRACT_VECTOR_ELT %2, %1
    %4:_(s32) = G_ANYEXT %3
    $vgpr0 = COPY %4
...

---
name: extract_vector_elt_v4s8_varidx_i32

body: |
  bb.0:
    liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4

    ; CHECK-LABEL: name: extract_vector_elt_v4s8_varidx_i32
    ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr4
    ; CHECK: [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY [[COPY]](<4 x s32>)
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
    ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<4 x s32>)
    ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[UV]], [[C]](s32)
    ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[UV1]], [[C]](s32)
    ; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[UV2]], [[C]](s32)
    ; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[UV3]], [[C]](s32)
    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
    ; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
    ; CHECK: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32)
    ; CHECK: [[ASHR3:%[0-9]+]]:_(s32) = G_ASHR [[SHL3]], [[C]](s32)
    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[ASHR]](s32), [[ASHR1]](s32), [[ASHR2]](s32), [[ASHR3]](s32)
    ; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<4 x s32>), [[COPY1]](s32)
    ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[EVEC]](s32)
    ; CHECK: $vgpr0 = COPY [[COPY3]](s32)
    %0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
    %1:_(s32) = COPY $vgpr4
    %2:_(<4 x s8>) = G_TRUNC %0
    %3:_(s8) = G_EXTRACT_VECTOR_ELT %2, %1
    %4:_(s32) = G_ANYEXT %3
    $vgpr0 = COPY %4
...

---
name: extract_vector_elt_v2s16_varidx_i32

body: |
  bb.0:
    liveins: $vgpr0, $vgpr1

    ; CHECK-LABEL: name: extract_vector_elt_v2s16_varidx_i32
    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
    ; CHECK: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x s16>), [[COPY1]](s32)
    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC]](s16)
    ; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)
    %0:_(<2 x s16>) = COPY $vgpr0
    %1:_(s32) = COPY $vgpr1
    %2:_(s16) = G_EXTRACT_VECTOR_ELT %0, %1
    %3:_(s32) = G_ANYEXT %2
    $vgpr0 = COPY %3
...

---
name: extract_vector_elt_v2s16_idx0_i32

body: |
  bb.0:
    liveins: $vgpr0

    ; CHECK-LABEL: name: extract_vector_elt_v2s16_idx0_i32
    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
    ; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
    ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
    %0:_(<2 x s16>) = COPY $vgpr0
    %1:_(s32) = G_CONSTANT i32 0
    %2:_(s16) = G_EXTRACT_VECTOR_ELT %0, %1
    %3:_(s32) = G_ANYEXT %2
    $vgpr0 = COPY %3
...

---
name: extract_vector_elt_v2s16_idx1_i32

body: |
  bb.0:
    liveins: $vgpr0

    ; CHECK-LABEL: name: extract_vector_elt_v2s16_idx1_i32
    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
    ; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
    ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
    ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
    %0:_(<2 x s16>) = COPY $vgpr0
    %1:_(s32) = G_CONSTANT i32 1
    %2:_(s16) = G_EXTRACT_VECTOR_ELT %0, %1
    %3:_(s32) = G_ANYEXT %2
    $vgpr0 = COPY %3
...

---
name: extract_vector_elt_v2s16_idx2_i32

body: |
  bb.0:
    liveins: $vgpr0

    ; CHECK-LABEL: name: extract_vector_elt_v2s16_idx2_i32
    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
    ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
    ; CHECK: $vgpr0 = COPY [[DEF]](s32)
    %0:_(<2 x s16>) = COPY $vgpr0
    %1:_(s32) = G_CONSTANT i32 2
    %2:_(s16) = G_EXTRACT_VECTOR_ELT %0, %1
    %3:_(s32) = G_ANYEXT %2
    $vgpr0 = COPY %3
...

---
name: extract_vector_elt_v3s16_varidx_i32

body: |
  bb.0:
    liveins: $vgpr0_vgpr1_vgpr2, $vgpr3

    ; CHECK-LABEL: name: extract_vector_elt_v3s16_varidx_i32
    ; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr3
    ; CHECK: [[COPY2:%[0-9]+]]:_(<3 x s32>) = COPY [[COPY]](<3 x s32>)
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
    ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<3 x s32>)
    ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[UV]], [[C]](s32)
    ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[UV1]], [[C]](s32)
    ; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[UV2]], [[C]](s32)
    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
    ; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
    ; CHECK: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32)
    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[ASHR]](s32), [[ASHR1]](s32), [[ASHR2]](s32)
    ; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<3 x s32>), [[COPY1]](s32)
    ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[EVEC]](s32)
    ; CHECK: $vgpr0 = COPY [[COPY3]](s32)
    %0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
    %1:_(s32) = COPY $vgpr3
    %2:_(<3 x s16>) = G_TRUNC %0
    %3:_(s16) = G_EXTRACT_VECTOR_ELT %2, %1
    %4:_(s32) = G_ANYEXT %3
    $vgpr0 = COPY %4
...

---
name: extract_vector_elt_v3s16_idx0_i32

body: |
  bb.0:
    liveins: $vgpr0_vgpr1_vgpr2

    ; CHECK-LABEL: name: extract_vector_elt_v3s16_idx0_i32
    ; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
    ; CHECK: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY [[COPY]](<3 x s32>)
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
    ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
    ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[UV]], [[C]](s32)
    ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[UV1]], [[C]](s32)
    ; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[UV2]], [[C]](s32)
    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
    ; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
    ; CHECK: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32)
    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[ASHR]](s32), [[ASHR1]](s32), [[ASHR2]](s32)
    ; CHECK: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[BUILD_VECTOR]](<3 x s32>), 0
    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[EXTRACT]](s32)
    ; CHECK: $vgpr0 = COPY [[COPY2]](s32)
    %0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
    %1:_(s32) = G_CONSTANT i32 0
    %2:_(<3 x s16>) = G_TRUNC %0
    %3:_(s16) = G_EXTRACT_VECTOR_ELT %2, %1
    %4:_(s32) = G_ANYEXT %3
    $vgpr0 = COPY %4
...

---
name: extract_vector_elt_v3s16_idx1_i32

body: |
  bb.0:
    liveins: $vgpr0_vgpr1_vgpr2

    ; CHECK-LABEL: name: extract_vector_elt_v3s16_idx1_i32
    ; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
    ; CHECK: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY [[COPY]](<3 x s32>)
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
    ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
    ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[UV]], [[C]](s32)
    ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[UV1]], [[C]](s32)
    ; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[UV2]], [[C]](s32)
    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
    ; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
    ; CHECK: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32)
    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[ASHR]](s32), [[ASHR1]](s32), [[ASHR2]](s32)
    ; CHECK: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[BUILD_VECTOR]](<3 x s32>), 32
    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[EXTRACT]](s32)
    ; CHECK: $vgpr0 = COPY [[COPY2]](s32)
    %0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
    %1:_(s32) = G_CONSTANT i32 1
    %2:_(<3 x s16>) = G_TRUNC %0
    %3:_(s16) = G_EXTRACT_VECTOR_ELT %2, %1
    %4:_(s32) = G_ANYEXT %3
    $vgpr0 = COPY %4
...

---
name: extract_vector_elt_v3s16_idx2_i32

body: |
  bb.0:
    liveins: $vgpr0_vgpr1_vgpr2

    ; CHECK-LABEL: name: extract_vector_elt_v3s16_idx2_i32
    ; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
    ; CHECK: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY [[COPY]](<3 x s32>)
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
    ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
    ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[UV]], [[C]](s32)
    ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[UV1]], [[C]](s32)
    ; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[UV2]], [[C]](s32)
    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
    ; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
    ; CHECK: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32)
    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[ASHR]](s32), [[ASHR1]](s32), [[ASHR2]](s32)
    ; CHECK: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[BUILD_VECTOR]](<3 x s32>), 64
    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[EXTRACT]](s32)
    ; CHECK: $vgpr0 = COPY [[COPY2]](s32)
    %0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
    %1:_(s32) = G_CONSTANT i32 2
    %2:_(<3 x s16>) = G_TRUNC %0
    %3:_(s16) = G_EXTRACT_VECTOR_ELT %2, %1
    %4:_(s32) = G_ANYEXT %3
    $vgpr0 = COPY %4
...

---
name: extract_vector_elt_v3s16_idx3_i32

body: |
  bb.0:
    liveins: $vgpr0_vgpr1_vgpr2

    ; CHECK-LABEL: name: extract_vector_elt_v3s16_idx3_i32
    ; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
    ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
    ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
    %0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
    %1:_(s32) = G_CONSTANT i32 3
    %2:_(<3 x s16>) = G_TRUNC %0
    %3:_(s16) = G_EXTRACT_VECTOR_ELT %2, %1
    %4:_(s32) = G_ANYEXT %3
    $vgpr0 = COPY %4
...

---
name: extract_vector_elt_v4s16_varidx_i32

body: |
  bb.0:
    liveins: $vgpr0_vgpr1, $vgpr2

    ; CHECK-LABEL: name: extract_vector_elt_v4s16_varidx_i32
    ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
    ; CHECK: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[COPY]](<4 x s16>), [[COPY1]](s32)
    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC]](s16)
    ; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)
    %0:_(<4 x s16>) = COPY $vgpr0_vgpr1
    %1:_(s32) = COPY $vgpr2
    %2:_(s16) = G_EXTRACT_VECTOR_ELT %0, %1
    %3:_(s32) = G_ANYEXT %2
    $vgpr0 = COPY %3
...

---
name: extract_vector_elt_v2s128_varidx_i32

body: |
  bb.0:
    liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8

    ; CHECK-LABEL: name: extract_vector_elt_v2s128_varidx_i32
    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s128>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr8
    ; CHECK: [[EVEC:%[0-9]+]]:_(s128) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x s128>), [[COPY1]](s32)
    ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[EVEC]](s128)
    %0:_(<2 x s128>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
    %1:_(s32) = COPY $vgpr8
    %2:_(s128) = G_EXTRACT_VECTOR_ELT %0, %1
    $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %2
...

---
name: extract_vector_elt_v2i32_varidx_i64

body: |
  bb.0:
    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3

    ; CHECK-LABEL: name: extract_vector_elt_v2i32_varidx_i64
    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
    ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
    ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
    ; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x s32>), [[TRUNC]](s32)
    ; CHECK: $vgpr0 = COPY [[EVEC]](s32)
    %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
    %1:_(s64) = COPY $vgpr2_vgpr3
    %2:_(s32) = G_EXTRACT_VECTOR_ELT %0, %1
    $vgpr0 = COPY %2
...
---
name: extract_vector_elt_0_v2i64

body: |
  bb.0:
    liveins: $vgpr0_vgpr1_vgpr2_vgpr3

    ; CHECK-LABEL: name: extract_vector_elt_0_v2i64
    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
    ; CHECK: [[EXTRACT:%[0-9]+]]:_(s64) = G_EXTRACT [[COPY]](<2 x s64>), 0
    ; CHECK: $vgpr0_vgpr1 = COPY [[EXTRACT]](s64)
    %0:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
    %1:_(s32) = G_CONSTANT i32 0
    %2:_(s64) = G_EXTRACT_VECTOR_ELT %0, %1
    $vgpr0_vgpr1 = COPY %2
...

---
name: extract_vector_elt_0_v8i64

body: |
  bb.0:
    liveins: $vgpr0_vgpr1_vgpr2_vgpr3

    ; CHECK-LABEL: name: extract_vector_elt_0_v8i64
    ; CHECK: [[DEF:%[0-9]+]]:_(<8 x s64>) = G_IMPLICIT_DEF
    ; CHECK: [[EXTRACT:%[0-9]+]]:_(s64) = G_EXTRACT [[DEF]](<8 x s64>), 0
    ; CHECK: $vgpr0_vgpr1 = COPY [[EXTRACT]](s64)
    %0:_(<8 x s64>) = G_IMPLICIT_DEF
    %1:_(s32) = G_CONSTANT i32 0
    %2:_(s64) = G_EXTRACT_VECTOR_ELT %0, %1
    $vgpr0_vgpr1 = COPY %2
...

---
name: extract_vector_elt_0_v16i64

body: |
  bb.0:
    liveins: $vgpr0_vgpr1_vgpr2_vgpr3

    ; CHECK-LABEL: name: extract_vector_elt_0_v16i64
    ; CHECK: [[DEF:%[0-9]+]]:_(<16 x s64>) = G_IMPLICIT_DEF
    ; CHECK: [[EXTRACT:%[0-9]+]]:_(s64) = G_EXTRACT [[DEF]](<16 x s64>), 0
    ; CHECK: $vgpr0_vgpr1 = COPY [[EXTRACT]](s64)
    %0:_(<16 x s64>) = G_IMPLICIT_DEF
    %1:_(s32) = G_CONSTANT i32 0
    %2:_(s64) = G_EXTRACT_VECTOR_ELT %0, %1
    $vgpr0_vgpr1 = COPY %2
...