test/CodeGen/AMDGPU/GlobalISel/inst-select-ptr-mask.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck %s

---
name:  ptr_mask_p3_sgpr_sgpr_1
legalized:       true
regBankSelected: true

body: |
  bb.0:
    liveins: $sgpr0

    ; CHECK-LABEL: name: ptr_mask_p3_sgpr_sgpr_1
    ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -2
    ; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
    ; CHECK: S_ENDPGM 0, implicit [[S_AND_B32_]]
    %0:sgpr(p3) = COPY $sgpr0
    %1:sgpr(p3) = G_PTR_MASK %0, 1
    S_ENDPGM 0, implicit %1

...

---
name:  ptr_mask_p3_sgpr_sgpr_2
legalized:       true
regBankSelected: true

body: |
  bb.0:
    liveins: $sgpr0

    ; CHECK-LABEL: name: ptr_mask_p3_sgpr_sgpr_2
    ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -4
    ; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
    ; CHECK: S_ENDPGM 0, implicit [[S_AND_B32_]]
    %0:sgpr(p3) = COPY $sgpr0
    %1:sgpr(p3) = G_PTR_MASK %0, 2
    S_ENDPGM 0, implicit %1

...

---
name:  ptr_mask_p3_sgpr_sgpr_3
legalized:       true
regBankSelected: true

body: |
  bb.0:
    liveins: $sgpr0

    ; CHECK-LABEL: name: ptr_mask_p3_sgpr_sgpr_3
    ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -8
    ; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
    ; CHECK: S_ENDPGM 0, implicit [[S_AND_B32_]]
    %0:sgpr(p3) = COPY $sgpr0
    %1:sgpr(p3) = G_PTR_MASK %0, 3
    S_ENDPGM 0, implicit %1

...

---
name:  ptr_mask_p3_sgpr_sgpr_4
legalized:       true
regBankSelected: true

body: |
  bb.0:
    liveins: $sgpr0

    ; CHECK-LABEL: name: ptr_mask_p3_sgpr_sgpr_4
    ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -16
    ; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
    ; CHECK: S_ENDPGM 0, implicit [[S_AND_B32_]]
    %0:sgpr(p3) = COPY $sgpr0
    %1:sgpr(p3) = G_PTR_MASK %0, 4
    S_ENDPGM 0, implicit %1

...

---
name:  ptr_mask_p3_sgpr_sgpr_29
legalized:       true
regBankSelected: true

body: |
  bb.0:
    liveins: $sgpr0

    ; CHECK-LABEL: name: ptr_mask_p3_sgpr_sgpr_29
    ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -16
    ; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
    ; CHECK: S_ENDPGM 0, implicit [[S_AND_B32_]]
    %0:sgpr(p3) = COPY $sgpr0
    %1:sgpr(p3) = G_PTR_MASK %0, 4
    S_ENDPGM 0, implicit %1

...

---
name:  ptr_mask_p0_sgpr_sgpr_1
legalized:       true
regBankSelected: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1

    ; CHECK-LABEL: name: ptr_mask_p0_sgpr_sgpr_1
    ; CHECK: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
    ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -2
    ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
    ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
    ; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
    ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[S_AND_B32_]], %subreg.sub0, [[COPY2]], %subreg.sub1
    ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
    %0:sgpr(p0) = COPY $sgpr0_sgpr1
    %1:sgpr(p0) = G_PTR_MASK %0, 1
    S_ENDPGM 0, implicit %1

...

---
name:  ptr_mask_p0_sgpr_sgpr_2
legalized:       true
regBankSelected: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1

    ; CHECK-LABEL: name: ptr_mask_p0_sgpr_sgpr_2
    ; CHECK: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
    ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -4
    ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
    ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
    ; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
    ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[S_AND_B32_]], %subreg.sub0, [[COPY2]], %subreg.sub1
    ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
    %0:sgpr(p0) = COPY $sgpr0_sgpr1
    %1:sgpr(p0) = G_PTR_MASK %0, 2
    S_ENDPGM 0, implicit %1

...

---
name:  ptr_mask_p0_sgpr_sgpr_3
legalized:       true
regBankSelected: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1

    ; CHECK-LABEL: name: ptr_mask_p0_sgpr_sgpr_3
    ; CHECK: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
    ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -8
    ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
    ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
    ; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
    ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[S_AND_B32_]], %subreg.sub0, [[COPY2]], %subreg.sub1
    ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
    %0:sgpr(p0) = COPY $sgpr0_sgpr1
    %1:sgpr(p0) = G_PTR_MASK %0, 3
    S_ENDPGM 0, implicit %1

...

---
name:  ptr_mask_p0_sgpr_sgpr_4
legalized:       true
regBankSelected: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1

    ; CHECK-LABEL: name: ptr_mask_p0_sgpr_sgpr_4
    ; CHECK: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
    ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -16
    ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
    ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
    ; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
    ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[S_AND_B32_]], %subreg.sub0, [[COPY2]], %subreg.sub1
    ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
    %0:sgpr(p0) = COPY $sgpr0_sgpr1
    %1:sgpr(p0) = G_PTR_MASK %0, 4
    S_ENDPGM 0, implicit %1

...

---
name:  ptr_mask_p0_sgpr_sgpr_29
legalized:       true
regBankSelected: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1

    ; CHECK-LABEL: name: ptr_mask_p0_sgpr_sgpr_29
    ; CHECK: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
    ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -16
    ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
    ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
    ; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
    ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[S_AND_B32_]], %subreg.sub0, [[COPY2]], %subreg.sub1
    ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
    %0:sgpr(p0) = COPY $sgpr0_sgpr1
    %1:sgpr(p0) = G_PTR_MASK %0, 4
    S_ENDPGM 0, implicit %1

...

---
name:  ptr_mask_p3_vgpr_vgpr_1
legalized:       true
regBankSelected: true

body: |
  bb.0:
    liveins: $vgpr0

    ; CHECK-LABEL: name: ptr_mask_p3_vgpr_vgpr_1
    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -2, implicit $exec
    ; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
    ; CHECK: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
    %0:vgpr(p3) = COPY $vgpr0
    %1:vgpr(p3) = G_PTR_MASK %0, 1
    S_ENDPGM 0, implicit %1

...

---
name:  ptr_mask_p3_vgpr_vgpr_2
legalized:       true
regBankSelected: true

body: |
  bb.0:
    liveins: $vgpr0

    ; CHECK-LABEL: name: ptr_mask_p3_vgpr_vgpr_2
    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -4, implicit $exec
    ; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
    ; CHECK: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
    %0:vgpr(p3) = COPY $vgpr0
    %1:vgpr(p3) = G_PTR_MASK %0, 2
    S_ENDPGM 0, implicit %1

...

---
name:  ptr_mask_p3_vgpr_vgpr_3
legalized:       true
regBankSelected: true

body: |
  bb.0:
    liveins: $vgpr0

    ; CHECK-LABEL: name: ptr_mask_p3_vgpr_vgpr_3
    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -4, implicit $exec
    ; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
    ; CHECK: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
    %0:vgpr(p3) = COPY $vgpr0
    %1:vgpr(p3) = G_PTR_MASK %0, 2
    S_ENDPGM 0, implicit %1

...

---
name:  ptr_mask_p3_vgpr_vgpr_4
legalized:       true
regBankSelected: true

body: |
  bb.0:
    liveins: $vgpr0

    ; CHECK-LABEL: name: ptr_mask_p3_vgpr_vgpr_4
    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -16, implicit $exec
    ; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
    ; CHECK: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
    %0:vgpr(p3) = COPY $vgpr0
    %1:vgpr(p3) = G_PTR_MASK %0, 4
    S_ENDPGM 0, implicit %1

...

---
name:  ptr_mask_p3_vgpr_vgpr_29
legalized:       true
regBankSelected: true

body: |
  bb.0:
    liveins: $vgpr0

    ; CHECK-LABEL: name: ptr_mask_p3_vgpr_vgpr_29
    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -16, implicit $exec
    ; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
    ; CHECK: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
    %0:vgpr(p3) = COPY $vgpr0
    %1:vgpr(p3) = G_PTR_MASK %0, 4
    S_ENDPGM 0, implicit %1

...

---
name:  ptr_mask_p0_vgpr_vgpr_1
legalized:       true
regBankSelected: true

body: |
  bb.0:
    liveins: $vgpr0_vgpr1

    ; CHECK-LABEL: name: ptr_mask_p0_vgpr_vgpr_1
    ; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -2, implicit $exec
    ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
    ; CHECK: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
    ; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec
    ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[COPY2]], %subreg.sub1
    ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
    %0:vgpr(p0) = COPY $vgpr0_vgpr1
    %1:vgpr(p0) = G_PTR_MASK %0, 1
    S_ENDPGM 0, implicit %1

...

---
name:  ptr_mask_p0_vgpr_vgpr_2
legalized:       true
regBankSelected: true

body: |
  bb.0:
    liveins: $vgpr0_vgpr1

    ; CHECK-LABEL: name: ptr_mask_p0_vgpr_vgpr_2
    ; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -4, implicit $exec
    ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
    ; CHECK: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
    ; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec
    ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[COPY2]], %subreg.sub1
    ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
    %0:vgpr(p0) = COPY $vgpr0_vgpr1
    %1:vgpr(p0) = G_PTR_MASK %0, 2
    S_ENDPGM 0, implicit %1

...

---
name:  ptr_mask_p0_vgpr_vgpr_3
legalized:       true
regBankSelected: true

body: |
  bb.0:
    liveins: $vgpr0_vgpr1

    ; CHECK-LABEL: name: ptr_mask_p0_vgpr_vgpr_3
    ; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -4, implicit $exec
    ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
    ; CHECK: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
    ; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec
    ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[COPY2]], %subreg.sub1
    ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
    %0:vgpr(p0) = COPY $vgpr0_vgpr1
    %1:vgpr(p0) = G_PTR_MASK %0, 2
    S_ENDPGM 0, implicit %1

...

---
name:  ptr_mask_p0_vgpr_vgpr_4
legalized:       true
regBankSelected: true

body: |
  bb.0:
    liveins: $vgpr0_vgpr1

    ; CHECK-LABEL: name: ptr_mask_p0_vgpr_vgpr_4
    ; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -16, implicit $exec
    ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
    ; CHECK: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
    ; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec
    ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[COPY2]], %subreg.sub1
    ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
    %0:vgpr(p0) = COPY $vgpr0_vgpr1
    %1:vgpr(p0) = G_PTR_MASK %0, 4
    S_ENDPGM 0, implicit %1

...

---
name:  ptr_mask_p0_vgpr_vgpr_29
legalized:       true
regBankSelected: true

body: |
  bb.0:
    liveins: $vgpr0_vgpr1

    ; CHECK-LABEL: name: ptr_mask_p0_vgpr_vgpr_29
    ; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -16, implicit $exec
    ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
    ; CHECK: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
    ; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec
    ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[COPY2]], %subreg.sub1
    ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
    %0:vgpr(p0) = COPY $vgpr0_vgpr1
    %1:vgpr(p0) = G_PTR_MASK %0, 4
    S_ENDPGM 0, implicit %1

...

---
name:  ptr_mask_p3_vgpr_sgpr_2
legalized:       true
regBankSelected: true

body: |
  bb.0:
    liveins: $sgpr0

    ; CHECK-LABEL: name: ptr_mask_p3_vgpr_sgpr_2
    ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -4, implicit $exec
    ; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
    ; CHECK: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
    %0:sgpr(p3) = COPY $sgpr0
    %1:vgpr(p3) = G_PTR_MASK %0, 2
    S_ENDPGM 0, implicit %1

...

---
name:  ptr_mask_p0_vgpr_sgpr_2
legalized:       true
regBankSelected: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1

    ; CHECK-LABEL: name: ptr_mask_p0_vgpr_sgpr_2
    ; CHECK: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
    ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -4, implicit $exec
    ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
    ; CHECK: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
    ; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec
    ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[COPY2]], %subreg.sub1
    ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
    %0:sgpr(p0) = COPY $sgpr0_sgpr1
    %1:vgpr(p0) = G_PTR_MASK %0, 2
    S_ENDPGM 0, implicit %1

...