test/CodeGen/AMDGPU/GlobalISel/inst-select-constant.mir

# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN

---

name:            constant
legalized:       true
regBankSelected: true
tracksRegLiveness: true


body: |
  bb.0:
    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
    ; GCN-LABEL: name: constant
    %0:vgpr(p1) = COPY $vgpr0_vgpr1
    %1:vgpr(p1) = COPY $vgpr2_vgpr3

    ; GCN: %{{[0-9]+}}:sreg_32 = S_MOV_B32 1
    %2:sreg_32(s32) = G_CONSTANT i32 1

    ; GCN: [[LO0:%[0-9]+]]:sreg_32 = S_MOV_B32 0
    ; GCN: [[HI0:%[0-9]+]]:sreg_32 = S_MOV_B32 1
    ; GCN: %{{[0-9]+}}:sreg_64_xexec = REG_SEQUENCE [[LO0]], %subreg.sub0, [[HI0]], %subreg.sub1
    %3:sgpr(s64) = G_CONSTANT i64 4294967296

    ; GCN: %{{[0-9]+}}:sreg_32 = S_MOV_B32 1065353216
    %4:sgpr(s32) = G_FCONSTANT float 1.0

    ; GCN: %5:sreg_64_xexec = S_MOV_B64 4607182418800017408
    %5:sgpr(s64) = G_FCONSTANT double 1.0

    ; GCN: [[LO1:%[0-9]+]]:sreg_32 = S_MOV_B32 0
    ; GCN: [[HI1:%[0-9]+]]:sreg_32 = S_MOV_B32 1076101120
    ; GCN: %{{[0-9]+}}:sreg_64_xexec = REG_SEQUENCE [[LO1]], %subreg.sub0, [[HI1]], %subreg.sub1
    %6:sgpr(s64) = G_FCONSTANT double 10.0

    ; GCN: %{{[0-9]+}}:vgpr_32 = V_MOV_B32_e32 1
    %7:vgpr(s32) = G_CONSTANT i32 1

    ; GCN: [[LO2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0
    ; GCN: [[HI2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1
    ; GCN: %{{[0-9]+}}:vreg_64 = REG_SEQUENCE [[LO2]], %subreg.sub0, [[HI2]], %subreg.sub1
    %8:vgpr(s64) = G_CONSTANT i64 4294967296

    ; GCN: %{{[0-9]+}}:vgpr_32 = V_MOV_B32_e32 1065353216
    %9:vgpr(s32) = G_FCONSTANT float 1.0

    ; GCN: [[LO3:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0
    ; GCN: [[HI3:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1072693248
    ; GCN: %{{[0-9]+}}:vreg_64 = REG_SEQUENCE [[LO3]], %subreg.sub0, [[HI3]], %subreg.sub1
    %10:vgpr(s64) = G_FCONSTANT double 1.0

    S_ENDPGM 0, implicit %2, implicit %4, implicit %5, implicit %6, implicit %8, implicit %3, implicit %5, implicit %7, implicit %9, implicit %10

...