test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmed3.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o -  | FileCheck -check-prefix=GCN %s

---
name: fmed3_s32_vvvv
legalized: true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins: $vgpr0, $vgpr1, $vgpr2

    ; GCN-LABEL: name: fmed3_s32_vvvv
    ; GCN: liveins: $vgpr0, $vgpr1, $vgpr2
    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
    ; GCN: [[V_MED3_F32_:%[0-9]+]]:vgpr_32 = V_MED3_F32 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
    ; GCN: S_ENDPGM 0, implicit [[V_MED3_F32_]]
    %0:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr1
    %2:vgpr(s32) = COPY $vgpr2
    %3:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %0, %1, %2
    S_ENDPGM 0, implicit %3
...

---
name: fmed3_s32_vsvv
legalized: true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins: $sgpr0, $vgpr0, $vgpr1

    ; GCN-LABEL: name: fmed3_s32_vsvv
    ; GCN: liveins: $sgpr0, $vgpr0, $vgpr1
    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GCN: [[V_MED3_F32_:%[0-9]+]]:vgpr_32 = V_MED3_F32 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
    ; GCN: S_ENDPGM 0, implicit [[V_MED3_F32_]]
    %0:sgpr(s32) = COPY $sgpr0
    %1:vgpr(s32) = COPY $vgpr0
    %2:vgpr(s32) = COPY $vgpr1
    %3:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %0, %1, %2
    S_ENDPGM 0, implicit %3
...

---
name: fmed3_s32_vvsv
legalized: true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins: $sgpr0, $vgpr0, $vgpr1

    ; GCN-LABEL: name: fmed3_s32_vvsv
    ; GCN: liveins: $sgpr0, $vgpr0, $vgpr1
    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GCN: [[V_MED3_F32_:%[0-9]+]]:vgpr_32 = V_MED3_F32 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
    ; GCN: S_ENDPGM 0, implicit [[V_MED3_F32_]]
    %0:vgpr(s32) = COPY $vgpr0
    %1:sgpr(s32) = COPY $sgpr0
    %2:vgpr(s32) = COPY $vgpr1
    %3:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %0, %1, %2
    S_ENDPGM 0, implicit %3
...

---
name: fmed3_s32_vvvs
legalized: true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins: $sgpr0, $vgpr0, $vgpr1

    ; GCN-LABEL: name: fmed3_s32_vvvs
    ; GCN: liveins: $sgpr0, $vgpr0, $vgpr1
    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GCN: [[V_MED3_F32_:%[0-9]+]]:vgpr_32 = V_MED3_F32 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
    ; GCN: S_ENDPGM 0, implicit [[V_MED3_F32_]]
    %0:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr0
    %2:sgpr(s32) = COPY $sgpr0
    %3:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %0, %1, %2
    S_ENDPGM 0, implicit %3
...


# Same SGPR used, so doesn't violate the constant bus restriction.
---
name: fmed3_s32_vssv
legalized: true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins: $sgpr0, $vgpr0

    ; GCN-LABEL: name: fmed3_s32_vssv
    ; GCN: liveins: $sgpr0, $vgpr0
    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN: [[V_MED3_F32_:%[0-9]+]]:vgpr_32 = V_MED3_F32 0, [[COPY]], 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
    ; GCN: S_ENDPGM 0, implicit [[V_MED3_F32_]]
    %0:sgpr(s32) = COPY $sgpr0
    %1:vgpr(s32) = COPY $vgpr0
    %2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %0, %0, %1
    S_ENDPGM 0, implicit %2
...

---
name: fmed3_s32_vsvs
legalized: true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins: $sgpr0, $vgpr0

    ; GCN-LABEL: name: fmed3_s32_vsvs
    ; GCN: liveins: $sgpr0, $vgpr0
    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN: [[V_MED3_F32_:%[0-9]+]]:vgpr_32 = V_MED3_F32 0, [[COPY]], 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec
    ; GCN: S_ENDPGM 0, implicit [[V_MED3_F32_]]
    %0:sgpr(s32) = COPY $sgpr0
    %1:vgpr(s32) = COPY $vgpr0
    %2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %0, %1, %0
    S_ENDPGM 0, implicit %2
...

---
name: fmed3_s32_vvss
legalized: true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins: $sgpr0, $vgpr0

    ; GCN-LABEL: name: fmed3_s32_vvss
    ; GCN: liveins: $sgpr0, $vgpr0
    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN: [[V_MED3_F32_:%[0-9]+]]:vgpr_32 = V_MED3_F32 0, [[COPY1]], 0, [[COPY]], 0, [[COPY]], 0, 0, implicit $exec
    ; GCN: S_ENDPGM 0, implicit [[V_MED3_F32_]]
    %0:sgpr(s32) = COPY $sgpr0
    %1:vgpr(s32) = COPY $vgpr0
    %2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %1, %0, %0
    S_ENDPGM 0, implicit %2
...

---
name: fmed3_s32_vsss
legalized: true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins: $sgpr0, $vgpr0

    ; GCN-LABEL: name: fmed3_s32_vsss
    ; GCN: liveins: $sgpr0, $vgpr0
    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GCN: [[V_MED3_F32_:%[0-9]+]]:vgpr_32 = V_MED3_F32 0, [[COPY]], 0, [[COPY]], 0, [[COPY]], 0, 0, implicit $exec
    ; GCN: S_ENDPGM 0, implicit [[V_MED3_F32_]]
    %0:sgpr(s32) = COPY $sgpr0
    %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %0, %0, %0
    S_ENDPGM 0, implicit %1
...


# FIXME: This should probably have been fixed by RegBankSelect, but we should fail to select it.
# ---
# name: fmed3_s32_vssv_constant_bus_violation
# legalized: true
# regBankSelected: true
# tracksRegLiveness: true

# body: |
#   bb.0:
#     liveins: $sgpr0, $sgpr1, $vgpr0

#     %0:sgpr(s32) = COPY $sgpr0
#     %1:sgpr(s32) = COPY $sgpr1
#     %2:vgpr(s32) = COPY $vgpr0
#     %3:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %0, %1, %2
#     S_ENDPGM 0, implicit %3
# ...