test/CodeGen/AArch64/GlobalISel/select-xor.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s

--- |
  target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"

  define void @xor_s32_gpr() { ret void }
  define void @xor_s64_gpr() { ret void }
  define void @xor_constant_n1_s32_gpr() { ret void }
  define void @xor_constant_n1_s64_gpr() { ret void }
  define void @xor_constant_n1_s32_gpr_2bb() { ret void }

...

---
# Check that we select a 32-bit GPR G_XOR into EORWrr on GPR32.
# Also check that we constrain the register class of the COPY to GPR32.
name:            xor_s32_gpr
legalized:       true
regBankSelected: true

registers:
  - { id: 0, class: gpr }
  - { id: 1, class: gpr }
  - { id: 2, class: gpr }

body:             |
  bb.0:
    liveins: $w0, $w1

    ; CHECK-LABEL: name: xor_s32_gpr
    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
    ; CHECK: [[EORWrr:%[0-9]+]]:gpr32 = EORWrr [[COPY]], [[COPY1]]
    ; CHECK: $w0 = COPY [[EORWrr]]
    %0(s32) = COPY $w0
    %1(s32) = COPY $w1
    %2(s32) = G_XOR %0, %1
    $w0 = COPY %2(s32)
...

---
# Same as xor_s64_gpr, for 64-bit operations.
name:            xor_s64_gpr
legalized:       true
regBankSelected: true

registers:
  - { id: 0, class: gpr }
  - { id: 1, class: gpr }
  - { id: 2, class: gpr }

body:             |
  bb.0:
    liveins: $x0, $x1

    ; CHECK-LABEL: name: xor_s64_gpr
    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
    ; CHECK: [[EORXrr:%[0-9]+]]:gpr64 = EORXrr [[COPY]], [[COPY1]]
    ; CHECK: $x0 = COPY [[EORXrr]]
    %0(s64) = COPY $x0
    %1(s64) = COPY $x1
    %2(s64) = G_XOR %0, %1
    $x0 = COPY %2(s64)
...

---
# Check that we select a 32-bit GPR G_XOR into EORWrr on GPR32.
# Also check that we constrain the register class of the COPY to GPR32.
name:            xor_constant_n1_s32_gpr
legalized:       true
regBankSelected: true

registers:
  - { id: 0, class: gpr }
  - { id: 1, class: gpr }
  - { id: 2, class: gpr }

body:             |
  bb.0:
    liveins: $w0

    ; CHECK-LABEL: name: xor_constant_n1_s32_gpr
    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
    ; CHECK: [[ORNWrr:%[0-9]+]]:gpr32 = ORNWrr $wzr, [[COPY]]
    ; CHECK: $w0 = COPY [[ORNWrr]]
    %0(s32) = COPY $w0
    %1(s32) = G_CONSTANT i32 -1
    %2(s32) = G_XOR %0, %1
    $w0 = COPY %2(s32)
...

---
# Same as xor_constant_n1_s64_gpr, for 64-bit operations.
name:            xor_constant_n1_s64_gpr
legalized:       true
regBankSelected: true

registers:
  - { id: 0, class: gpr }
  - { id: 1, class: gpr }
  - { id: 2, class: gpr }

body:             |
  bb.0:
    liveins: $x0

    ; CHECK-LABEL: name: xor_constant_n1_s64_gpr
    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
    ; CHECK: [[ORNXrr:%[0-9]+]]:gpr64 = ORNXrr $xzr, [[COPY]]
    ; CHECK: $x0 = COPY [[ORNXrr]]
    %0(s64) = COPY $x0
    %1(s64) = G_CONSTANT i64 -1
    %2(s64) = G_XOR %0, %1
    $x0 = COPY %2(s64)
...

---
# Check that we can obtain constants from other basic blocks.
name:            xor_constant_n1_s32_gpr_2bb
legalized:       true
regBankSelected: true

registers:
  - { id: 0, class: gpr }
  - { id: 1, class: gpr }
  - { id: 2, class: gpr }


body:             |
  ; CHECK-LABEL: name: xor_constant_n1_s32_gpr_2bb
  ; CHECK: bb.0:
  ; CHECK:   successors: %bb.1(0x80000000)
  ; CHECK:   B %bb.1
  ; CHECK: bb.1:
  ; CHECK:   [[COPY:%[0-9]+]]:gpr32 = COPY $w0
  ; CHECK:   [[ORNWrr:%[0-9]+]]:gpr32 = ORNWrr $wzr, [[COPY]]
  ; CHECK:   $w0 = COPY [[ORNWrr]]
  bb.0:
    liveins: $w0, $w1
    successors: %bb.1
    %1(s32) = G_CONSTANT i32 -1
    G_BR %bb.1
  bb.1:
    %0(s32) = COPY $w0
    %2(s32) = G_XOR %0, %1
    $w0 = COPY %2(s32)
...