test/CodeGen/AArch64/GlobalISel/select-vector-icmp.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s

--- |
  ; ModuleID = 'icmp-autogen-tests-with-ne.ll'
  source_filename = "icmp-autogen-tests-with-ne.ll"
  target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
  target triple = "aarch64"

  define <2 x i1> @test_v2i64_eq(<2 x i64> %v1, <2 x i64> %v2) {
    %cmp = icmp eq <2 x i64> %v1, %v2
    ret <2 x i1> %cmp
  }

  define <4 x i1> @test_v4i32_eq(<4 x i32> %v1, <4 x i32> %v2) {
    %cmp = icmp eq <4 x i32> %v1, %v2
    ret <4 x i1> %cmp
  }

  define <2 x i1> @test_v2i32_eq(<2 x i32> %v1, <2 x i32> %v2) {
    %cmp = icmp eq <2 x i32> %v1, %v2
    ret <2 x i1> %cmp
  }

  define <2 x i1> @test_v2i16_eq(<2 x i16> %v1, <2 x i16> %v2) {
    %cmp = icmp eq <2 x i16> %v1, %v2
    ret <2 x i1> %cmp
  }

  define <8 x i1> @test_v8i16_eq(<8 x i16> %v1, <8 x i16> %v2) {
    %cmp = icmp eq <8 x i16> %v1, %v2
    ret <8 x i1> %cmp
  }

  define <4 x i1> @test_v4i16_eq(<4 x i16> %v1, <4 x i16> %v2) {
    %cmp = icmp eq <4 x i16> %v1, %v2
    ret <4 x i1> %cmp
  }

  define <16 x i1> @test_v16i8_eq(<16 x i8> %v1, <16 x i8> %v2) {
    %cmp = icmp eq <16 x i8> %v1, %v2
    ret <16 x i1> %cmp
  }

  define <8 x i1> @test_v8i8_eq(<8 x i8> %v1, <8 x i8> %v2) {
    %cmp = icmp eq <8 x i8> %v1, %v2
    ret <8 x i1> %cmp
  }

  define <2 x i1> @test_v2i64_ne(<2 x i64> %v1, <2 x i64> %v2) {
    %cmp = icmp ne <2 x i64> %v1, %v2
    ret <2 x i1> %cmp
  }

  define <4 x i1> @test_v4i32_ne(<4 x i32> %v1, <4 x i32> %v2) {
    %cmp = icmp ne <4 x i32> %v1, %v2
    ret <4 x i1> %cmp
  }

  define <2 x i1> @test_v2i32_ne(<2 x i32> %v1, <2 x i32> %v2) {
    %cmp = icmp ne <2 x i32> %v1, %v2
    ret <2 x i1> %cmp
  }

  define <2 x i1> @test_v2i16_ne(<2 x i16> %v1, <2 x i16> %v2) {
    %cmp = icmp ne <2 x i16> %v1, %v2
    ret <2 x i1> %cmp
  }

  define <8 x i1> @test_v8i16_ne(<8 x i16> %v1, <8 x i16> %v2) {
    %cmp = icmp ne <8 x i16> %v1, %v2
    ret <8 x i1> %cmp
  }

  define <4 x i1> @test_v4i16_ne(<4 x i16> %v1, <4 x i16> %v2) {
    %cmp = icmp ne <4 x i16> %v1, %v2
    ret <4 x i1> %cmp
  }

  define <16 x i1> @test_v16i8_ne(<16 x i8> %v1, <16 x i8> %v2) {
    %cmp = icmp ne <16 x i8> %v1, %v2
    ret <16 x i1> %cmp
  }

  define <8 x i1> @test_v8i8_ne(<8 x i8> %v1, <8 x i8> %v2) {
    %cmp = icmp ne <8 x i8> %v1, %v2
    ret <8 x i1> %cmp
  }

  define <2 x i1> @test_v2i64_ugt(<2 x i64> %v1, <2 x i64> %v2) {
    %cmp = icmp ugt <2 x i64> %v1, %v2
    ret <2 x i1> %cmp
  }

  define <4 x i1> @test_v4i32_ugt(<4 x i32> %v1, <4 x i32> %v2) {
    %cmp = icmp ugt <4 x i32> %v1, %v2
    ret <4 x i1> %cmp
  }

  define <2 x i1> @test_v2i32_ugt(<2 x i32> %v1, <2 x i32> %v2) {
    %cmp = icmp ugt <2 x i32> %v1, %v2
    ret <2 x i1> %cmp
  }

  define <2 x i1> @test_v2i16_ugt(<2 x i16> %v1, <2 x i16> %v2) {
    %cmp = icmp ugt <2 x i16> %v1, %v2
    ret <2 x i1> %cmp
  }

  define <8 x i1> @test_v8i16_ugt(<8 x i16> %v1, <8 x i16> %v2) {
    %cmp = icmp ugt <8 x i16> %v1, %v2
    ret <8 x i1> %cmp
  }

  define <4 x i1> @test_v4i16_ugt(<4 x i16> %v1, <4 x i16> %v2) {
    %cmp = icmp ugt <4 x i16> %v1, %v2
    ret <4 x i1> %cmp
  }

  define <16 x i1> @test_v16i8_ugt(<16 x i8> %v1, <16 x i8> %v2) {
    %cmp = icmp ugt <16 x i8> %v1, %v2
    ret <16 x i1> %cmp
  }

  define <8 x i1> @test_v8i8_ugt(<8 x i8> %v1, <8 x i8> %v2) {
    %cmp = icmp ugt <8 x i8> %v1, %v2
    ret <8 x i1> %cmp
  }

  define <2 x i1> @test_v2i64_uge(<2 x i64> %v1, <2 x i64> %v2) {
    %cmp = icmp uge <2 x i64> %v1, %v2
    ret <2 x i1> %cmp
  }

  define <4 x i1> @test_v4i32_uge(<4 x i32> %v1, <4 x i32> %v2) {
    %cmp = icmp uge <4 x i32> %v1, %v2
    ret <4 x i1> %cmp
  }

  define <2 x i1> @test_v2i32_uge(<2 x i32> %v1, <2 x i32> %v2) {
    %cmp = icmp uge <2 x i32> %v1, %v2
    ret <2 x i1> %cmp
  }

  define <2 x i1> @test_v2i16_uge(<2 x i16> %v1, <2 x i16> %v2) {
    %cmp = icmp uge <2 x i16> %v1, %v2
    ret <2 x i1> %cmp
  }

  define <8 x i1> @test_v8i16_uge(<8 x i16> %v1, <8 x i16> %v2) {
    %cmp = icmp uge <8 x i16> %v1, %v2
    ret <8 x i1> %cmp
  }

  define <4 x i1> @test_v4i16_uge(<4 x i16> %v1, <4 x i16> %v2) {
    %cmp = icmp uge <4 x i16> %v1, %v2
    ret <4 x i1> %cmp
  }

  define <16 x i1> @test_v16i8_uge(<16 x i8> %v1, <16 x i8> %v2) {
    %cmp = icmp uge <16 x i8> %v1, %v2
    ret <16 x i1> %cmp
  }

  define <8 x i1> @test_v8i8_uge(<8 x i8> %v1, <8 x i8> %v2) {
    %cmp = icmp uge <8 x i8> %v1, %v2
    ret <8 x i1> %cmp
  }

  define <2 x i1> @test_v2i64_ult(<2 x i64> %v1, <2 x i64> %v2) {
    %cmp = icmp ult <2 x i64> %v1, %v2
    ret <2 x i1> %cmp
  }

  define <4 x i1> @test_v4i32_ult(<4 x i32> %v1, <4 x i32> %v2) {
    %cmp = icmp ult <4 x i32> %v1, %v2
    ret <4 x i1> %cmp
  }

  define <2 x i1> @test_v2i32_ult(<2 x i32> %v1, <2 x i32> %v2) {
    %cmp = icmp ult <2 x i32> %v1, %v2
    ret <2 x i1> %cmp
  }

  define <2 x i1> @test_v2i16_ult(<2 x i16> %v1, <2 x i16> %v2) {
    %cmp = icmp ult <2 x i16> %v1, %v2
    ret <2 x i1> %cmp
  }

  define <8 x i1> @test_v8i16_ult(<8 x i16> %v1, <8 x i16> %v2) {
    %cmp = icmp ult <8 x i16> %v1, %v2
    ret <8 x i1> %cmp
  }

  define <4 x i1> @test_v4i16_ult(<4 x i16> %v1, <4 x i16> %v2) {
    %cmp = icmp ult <4 x i16> %v1, %v2
    ret <4 x i1> %cmp
  }

  define <16 x i1> @test_v16i8_ult(<16 x i8> %v1, <16 x i8> %v2) {
    %cmp = icmp ult <16 x i8> %v1, %v2
    ret <16 x i1> %cmp
  }

  define <8 x i1> @test_v8i8_ult(<8 x i8> %v1, <8 x i8> %v2) {
    %cmp = icmp ult <8 x i8> %v1, %v2
    ret <8 x i1> %cmp
  }

  define <2 x i1> @test_v2i64_ule(<2 x i64> %v1, <2 x i64> %v2) {
    %cmp = icmp ule <2 x i64> %v1, %v2
    ret <2 x i1> %cmp
  }

  define <4 x i1> @test_v4i32_ule(<4 x i32> %v1, <4 x i32> %v2) {
    %cmp = icmp ule <4 x i32> %v1, %v2
    ret <4 x i1> %cmp
  }

  define <2 x i1> @test_v2i32_ule(<2 x i32> %v1, <2 x i32> %v2) {
    %cmp = icmp ule <2 x i32> %v1, %v2
    ret <2 x i1> %cmp
  }

  define <2 x i1> @test_v2i16_ule(<2 x i16> %v1, <2 x i16> %v2) {
    %cmp = icmp ule <2 x i16> %v1, %v2
    ret <2 x i1> %cmp
  }

  define <8 x i1> @test_v8i16_ule(<8 x i16> %v1, <8 x i16> %v2) {
    %cmp = icmp ule <8 x i16> %v1, %v2
    ret <8 x i1> %cmp
  }

  define <4 x i1> @test_v4i16_ule(<4 x i16> %v1, <4 x i16> %v2) {
    %cmp = icmp ule <4 x i16> %v1, %v2
    ret <4 x i1> %cmp
  }

  define <16 x i1> @test_v16i8_ule(<16 x i8> %v1, <16 x i8> %v2) {
    %cmp = icmp ule <16 x i8> %v1, %v2
    ret <16 x i1> %cmp
  }

  define <8 x i1> @test_v8i8_ule(<8 x i8> %v1, <8 x i8> %v2) {
    %cmp = icmp ule <8 x i8> %v1, %v2
    ret <8 x i1> %cmp
  }

  define <2 x i1> @test_v2i64_sgt(<2 x i64> %v1, <2 x i64> %v2) {
    %cmp = icmp sgt <2 x i64> %v1, %v2
    ret <2 x i1> %cmp
  }

  define <4 x i1> @test_v4i32_sgt(<4 x i32> %v1, <4 x i32> %v2) {
    %cmp = icmp sgt <4 x i32> %v1, %v2
    ret <4 x i1> %cmp
  }

  define <2 x i1> @test_v2i32_sgt(<2 x i32> %v1, <2 x i32> %v2) {
    %cmp = icmp sgt <2 x i32> %v1, %v2
    ret <2 x i1> %cmp
  }

  define <2 x i1> @test_v2i16_sgt(<2 x i16> %v1, <2 x i16> %v2) {
    %cmp = icmp sgt <2 x i16> %v1, %v2
    ret <2 x i1> %cmp
  }

  define <8 x i1> @test_v8i16_sgt(<8 x i16> %v1, <8 x i16> %v2) {
    %cmp = icmp sgt <8 x i16> %v1, %v2
    ret <8 x i1> %cmp
  }

  define <4 x i1> @test_v4i16_sgt(<4 x i16> %v1, <4 x i16> %v2) {
    %cmp = icmp sgt <4 x i16> %v1, %v2
    ret <4 x i1> %cmp
  }

  define <16 x i1> @test_v16i8_sgt(<16 x i8> %v1, <16 x i8> %v2) {
    %cmp = icmp sgt <16 x i8> %v1, %v2
    ret <16 x i1> %cmp
  }

  define <8 x i1> @test_v8i8_sgt(<8 x i8> %v1, <8 x i8> %v2) {
    %cmp = icmp sgt <8 x i8> %v1, %v2
    ret <8 x i1> %cmp
  }

  define <2 x i1> @test_v2i64_sge(<2 x i64> %v1, <2 x i64> %v2) {
    %cmp = icmp sge <2 x i64> %v1, %v2
    ret <2 x i1> %cmp
  }

  define <4 x i1> @test_v4i32_sge(<4 x i32> %v1, <4 x i32> %v2) {
    %cmp = icmp sge <4 x i32> %v1, %v2
    ret <4 x i1> %cmp
  }

  define <2 x i1> @test_v2i32_sge(<2 x i32> %v1, <2 x i32> %v2) {
    %cmp = icmp sge <2 x i32> %v1, %v2
    ret <2 x i1> %cmp
  }

  define <2 x i1> @test_v2i16_sge(<2 x i16> %v1, <2 x i16> %v2) {
    %cmp = icmp sge <2 x i16> %v1, %v2
    ret <2 x i1> %cmp
  }

  define <8 x i1> @test_v8i16_sge(<8 x i16> %v1, <8 x i16> %v2) {
    %cmp = icmp sge <8 x i16> %v1, %v2
    ret <8 x i1> %cmp
  }

  define <4 x i1> @test_v4i16_sge(<4 x i16> %v1, <4 x i16> %v2) {
    %cmp = icmp sge <4 x i16> %v1, %v2
    ret <4 x i1> %cmp
  }

  define <16 x i1> @test_v16i8_sge(<16 x i8> %v1, <16 x i8> %v2) {
    %cmp = icmp sge <16 x i8> %v1, %v2
    ret <16 x i1> %cmp
  }

  define <8 x i1> @test_v8i8_sge(<8 x i8> %v1, <8 x i8> %v2) {
    %cmp = icmp sge <8 x i8> %v1, %v2
    ret <8 x i1> %cmp
  }

  define <2 x i1> @test_v2i64_slt(<2 x i64> %v1, <2 x i64> %v2) {
    %cmp = icmp slt <2 x i64> %v1, %v2
    ret <2 x i1> %cmp
  }

  define <4 x i1> @test_v4i32_slt(<4 x i32> %v1, <4 x i32> %v2) {
    %cmp = icmp slt <4 x i32> %v1, %v2
    ret <4 x i1> %cmp
  }

  define <2 x i1> @test_v2i32_slt(<2 x i32> %v1, <2 x i32> %v2) {
    %cmp = icmp slt <2 x i32> %v1, %v2
    ret <2 x i1> %cmp
  }

  define <2 x i1> @test_v2i16_slt(<2 x i16> %v1, <2 x i16> %v2) {
    %cmp = icmp slt <2 x i16> %v1, %v2
    ret <2 x i1> %cmp
  }

  define <8 x i1> @test_v8i16_slt(<8 x i16> %v1, <8 x i16> %v2) {
    %cmp = icmp slt <8 x i16> %v1, %v2
    ret <8 x i1> %cmp
  }

  define <4 x i1> @test_v4i16_slt(<4 x i16> %v1, <4 x i16> %v2) {
    %cmp = icmp slt <4 x i16> %v1, %v2
    ret <4 x i1> %cmp
  }

  define <16 x i1> @test_v16i8_slt(<16 x i8> %v1, <16 x i8> %v2) {
    %cmp = icmp slt <16 x i8> %v1, %v2
    ret <16 x i1> %cmp
  }

  define <8 x i1> @test_v8i8_slt(<8 x i8> %v1, <8 x i8> %v2) {
    %cmp = icmp slt <8 x i8> %v1, %v2
    ret <8 x i1> %cmp
  }

  define <2 x i1> @test_v2i64_sle(<2 x i64> %v1, <2 x i64> %v2) {
    %cmp = icmp sle <2 x i64> %v1, %v2
    ret <2 x i1> %cmp
  }

  define <4 x i1> @test_v4i32_sle(<4 x i32> %v1, <4 x i32> %v2) {
    %cmp = icmp sle <4 x i32> %v1, %v2
    ret <4 x i1> %cmp
  }

  define <2 x i1> @test_v2i32_sle(<2 x i32> %v1, <2 x i32> %v2) {
    %cmp = icmp sle <2 x i32> %v1, %v2
    ret <2 x i1> %cmp
  }

  define <2 x i1> @test_v2i16_sle(<2 x i16> %v1, <2 x i16> %v2) {
    %cmp = icmp sle <2 x i16> %v1, %v2
    ret <2 x i1> %cmp
  }

  define <8 x i1> @test_v8i16_sle(<8 x i16> %v1, <8 x i16> %v2) {
    %cmp = icmp sle <8 x i16> %v1, %v2
    ret <8 x i1> %cmp
  }

  define <4 x i1> @test_v4i16_sle(<4 x i16> %v1, <4 x i16> %v2) {
    %cmp = icmp sle <4 x i16> %v1, %v2
    ret <4 x i1> %cmp
  }

  define <16 x i1> @test_v16i8_sle(<16 x i8> %v1, <16 x i8> %v2) {
    %cmp = icmp sle <16 x i8> %v1, %v2
    ret <16 x i1> %cmp
  }

  define <8 x i1> @test_v8i8_sle(<8 x i8> %v1, <8 x i8> %v2) {
    %cmp = icmp sle <8 x i8> %v1, %v2
    ret <8 x i1> %cmp
  }

...
---
name:            test_v2i64_eq
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v2i64_eq
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
    ; CHECK: [[CMEQv2i64_:%[0-9]+]]:fpr128 = CMEQv2i64 [[COPY]], [[COPY1]]
    ; CHECK: [[XTNv2i32_:%[0-9]+]]:fpr64 = XTNv2i32 [[CMEQv2i64_]]
    ; CHECK: $d0 = COPY [[XTNv2i32_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %0:fpr(<2 x s64>) = COPY $q0
    %1:fpr(<2 x s64>) = COPY $q1
    %4:fpr(<2 x s64>) = G_ICMP intpred(eq), %0(<2 x s64>), %1
    %3:fpr(<2 x s32>) = G_TRUNC %4(<2 x s64>)
    $d0 = COPY %3(<2 x s32>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v4i32_eq
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v4i32_eq
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
    ; CHECK: [[CMEQv4i32_:%[0-9]+]]:fpr128 = CMEQv4i32 [[COPY]], [[COPY1]]
    ; CHECK: [[XTNv4i16_:%[0-9]+]]:fpr64 = XTNv4i16 [[CMEQv4i32_]]
    ; CHECK: $d0 = COPY [[XTNv4i16_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %0:fpr(<4 x s32>) = COPY $q0
    %1:fpr(<4 x s32>) = COPY $q1
    %4:fpr(<4 x s32>) = G_ICMP intpred(eq), %0(<4 x s32>), %1
    %3:fpr(<4 x s16>) = G_TRUNC %4(<4 x s32>)
    $d0 = COPY %3(<4 x s16>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v2i32_eq
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $d0, $d1

    ; CHECK-LABEL: name: test_v2i32_eq
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
    ; CHECK: [[CMEQv2i32_:%[0-9]+]]:fpr64 = CMEQv2i32 [[COPY]], [[COPY1]]
    ; CHECK: $d0 = COPY [[CMEQv2i32_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %0:fpr(<2 x s32>) = COPY $d0
    %1:fpr(<2 x s32>) = COPY $d1
    %4:fpr(<2 x s32>) = G_ICMP intpred(eq), %0(<2 x s32>), %1
    %3:fpr(<2 x s32>) = COPY %4(<2 x s32>)
    $d0 = COPY %3(<2 x s32>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v2i16_eq
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: fpr }
  - { id: 3, class: fpr }
  - { id: 4, class: _ }
  - { id: 5, class: fpr }
  - { id: 6, class: _ }
  - { id: 7, class: fpr }
  - { id: 8, class: fpr }
  - { id: 9, class: fpr }
  - { id: 10, class: gpr }
  - { id: 11, class: fpr }
  - { id: 12, class: fpr }
  - { id: 13, class: gpr }
  - { id: 14, class: fpr }
  - { id: 15, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $d0, $d1

    ; CHECK-LABEL: name: test_v2i16_eq
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
    ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 65535
    ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[MOVi32imm]], %subreg.ssub
    ; CHECK: [[INSvi32gpr:%[0-9]+]]:fpr128 = INSvi32gpr [[INSERT_SUBREG]], 1, [[MOVi32imm]]
    ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi32gpr]].dsub
    ; CHECK: [[ANDv8i8_:%[0-9]+]]:fpr64 = ANDv8i8 [[COPY]], [[COPY2]]
    ; CHECK: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 65535
    ; CHECK: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
    ; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[MOVi32imm1]], %subreg.ssub
    ; CHECK: [[INSvi32gpr1:%[0-9]+]]:fpr128 = INSvi32gpr [[INSERT_SUBREG1]], 1, [[MOVi32imm1]]
    ; CHECK: [[COPY3:%[0-9]+]]:fpr64 = COPY [[INSvi32gpr1]].dsub
    ; CHECK: [[ANDv8i8_1:%[0-9]+]]:fpr64 = ANDv8i8 [[COPY1]], [[COPY3]]
    ; CHECK: [[CMEQv2i32_:%[0-9]+]]:fpr64 = CMEQv2i32 [[ANDv8i8_]], [[ANDv8i8_1]]
    ; CHECK: $d0 = COPY [[CMEQv2i32_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %2:fpr(<2 x s32>) = COPY $d0
    %3:fpr(<2 x s32>) = COPY $d1
    %13:gpr(s32) = G_CONSTANT i32 65535
    %14:fpr(<2 x s32>) = G_BUILD_VECTOR %13(s32), %13(s32)
    %15:fpr(<2 x s32>) = COPY %2(<2 x s32>)
    %7:fpr(<2 x s32>) = G_AND %15, %14
    %10:gpr(s32) = G_CONSTANT i32 65535
    %11:fpr(<2 x s32>) = G_BUILD_VECTOR %10(s32), %10(s32)
    %12:fpr(<2 x s32>) = COPY %3(<2 x s32>)
    %8:fpr(<2 x s32>) = G_AND %12, %11
    %9:fpr(<2 x s32>) = G_ICMP intpred(eq), %7(<2 x s32>), %8
    %5:fpr(<2 x s32>) = COPY %9(<2 x s32>)
    $d0 = COPY %5(<2 x s32>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v8i16_eq
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v8i16_eq
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
    ; CHECK: [[CMEQv8i16_:%[0-9]+]]:fpr128 = CMEQv8i16 [[COPY]], [[COPY1]]
    ; CHECK: [[XTNv8i8_:%[0-9]+]]:fpr64 = XTNv8i8 [[CMEQv8i16_]]
    ; CHECK: $d0 = COPY [[XTNv8i8_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %0:fpr(<8 x s16>) = COPY $q0
    %1:fpr(<8 x s16>) = COPY $q1
    %4:fpr(<8 x s16>) = G_ICMP intpred(eq), %0(<8 x s16>), %1
    %3:fpr(<8 x s8>) = G_TRUNC %4(<8 x s16>)
    $d0 = COPY %3(<8 x s8>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v4i16_eq
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $d0, $d1

    ; CHECK-LABEL: name: test_v4i16_eq
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
    ; CHECK: [[CMEQv4i16_:%[0-9]+]]:fpr64 = CMEQv4i16 [[COPY]], [[COPY1]]
    ; CHECK: $d0 = COPY [[CMEQv4i16_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %0:fpr(<4 x s16>) = COPY $d0
    %1:fpr(<4 x s16>) = COPY $d1
    %4:fpr(<4 x s16>) = G_ICMP intpred(eq), %0(<4 x s16>), %1
    %3:fpr(<4 x s16>) = COPY %4(<4 x s16>)
    $d0 = COPY %3(<4 x s16>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v16i8_eq
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v16i8_eq
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
    ; CHECK: [[CMEQv16i8_:%[0-9]+]]:fpr128 = CMEQv16i8 [[COPY]], [[COPY1]]
    ; CHECK: $q0 = COPY [[CMEQv16i8_]]
    ; CHECK: RET_ReallyLR implicit $q0
    %0:fpr(<16 x s8>) = COPY $q0
    %1:fpr(<16 x s8>) = COPY $q1
    %4:fpr(<16 x s8>) = G_ICMP intpred(eq), %0(<16 x s8>), %1
    %3:fpr(<16 x s8>) = COPY %4(<16 x s8>)
    $q0 = COPY %3(<16 x s8>)
    RET_ReallyLR implicit $q0

...
---
name:            test_v8i8_eq
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $d0, $d1

    ; CHECK-LABEL: name: test_v8i8_eq
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
    ; CHECK: [[CMEQv8i8_:%[0-9]+]]:fpr64 = CMEQv8i8 [[COPY]], [[COPY1]]
    ; CHECK: $d0 = COPY [[CMEQv8i8_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %0:fpr(<8 x s8>) = COPY $d0
    %1:fpr(<8 x s8>) = COPY $d1
    %4:fpr(<8 x s8>) = G_ICMP intpred(eq), %0(<8 x s8>), %1
    %3:fpr(<8 x s8>) = COPY %4(<8 x s8>)
    $d0 = COPY %3(<8 x s8>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v2i64_ne
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v2i64_ne
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
    ; CHECK: [[CMEQv2i64_:%[0-9]+]]:fpr128 = CMEQv2i64 [[COPY]], [[COPY1]]
    ; CHECK: [[NOTv16i8_:%[0-9]+]]:fpr128 = NOTv16i8 [[CMEQv2i64_]]
    ; CHECK: [[XTNv2i32_:%[0-9]+]]:fpr64 = XTNv2i32 [[NOTv16i8_]]
    ; CHECK: $d0 = COPY [[XTNv2i32_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %0:fpr(<2 x s64>) = COPY $q0
    %1:fpr(<2 x s64>) = COPY $q1
    %4:fpr(<2 x s64>) = G_ICMP intpred(ne), %0(<2 x s64>), %1
    %3:fpr(<2 x s32>) = G_TRUNC %4(<2 x s64>)
    $d0 = COPY %3(<2 x s32>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v4i32_ne
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v4i32_ne
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
    ; CHECK: [[CMEQv4i32_:%[0-9]+]]:fpr128 = CMEQv4i32 [[COPY]], [[COPY1]]
    ; CHECK: [[NOTv16i8_:%[0-9]+]]:fpr128 = NOTv16i8 [[CMEQv4i32_]]
    ; CHECK: [[XTNv4i16_:%[0-9]+]]:fpr64 = XTNv4i16 [[NOTv16i8_]]
    ; CHECK: $d0 = COPY [[XTNv4i16_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %0:fpr(<4 x s32>) = COPY $q0
    %1:fpr(<4 x s32>) = COPY $q1
    %4:fpr(<4 x s32>) = G_ICMP intpred(ne), %0(<4 x s32>), %1
    %3:fpr(<4 x s16>) = G_TRUNC %4(<4 x s32>)
    $d0 = COPY %3(<4 x s16>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v2i32_ne
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $d0, $d1

    ; CHECK-LABEL: name: test_v2i32_ne
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
    ; CHECK: [[CMEQv2i32_:%[0-9]+]]:fpr64 = CMEQv2i32 [[COPY]], [[COPY1]]
    ; CHECK: [[NOTv8i8_:%[0-9]+]]:fpr64 = NOTv8i8 [[CMEQv2i32_]]
    ; CHECK: $d0 = COPY [[NOTv8i8_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %0:fpr(<2 x s32>) = COPY $d0
    %1:fpr(<2 x s32>) = COPY $d1
    %4:fpr(<2 x s32>) = G_ICMP intpred(ne), %0(<2 x s32>), %1
    %3:fpr(<2 x s32>) = COPY %4(<2 x s32>)
    $d0 = COPY %3(<2 x s32>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v2i16_ne
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: fpr }
  - { id: 3, class: fpr }
  - { id: 4, class: _ }
  - { id: 5, class: fpr }
  - { id: 6, class: _ }
  - { id: 7, class: fpr }
  - { id: 8, class: fpr }
  - { id: 9, class: fpr }
  - { id: 10, class: gpr }
  - { id: 11, class: fpr }
  - { id: 12, class: fpr }
  - { id: 13, class: gpr }
  - { id: 14, class: fpr }
  - { id: 15, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $d0, $d1

    ; CHECK-LABEL: name: test_v2i16_ne
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
    ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 65535
    ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[MOVi32imm]], %subreg.ssub
    ; CHECK: [[INSvi32gpr:%[0-9]+]]:fpr128 = INSvi32gpr [[INSERT_SUBREG]], 1, [[MOVi32imm]]
    ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi32gpr]].dsub
    ; CHECK: [[ANDv8i8_:%[0-9]+]]:fpr64 = ANDv8i8 [[COPY]], [[COPY2]]
    ; CHECK: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 65535
    ; CHECK: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
    ; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[MOVi32imm1]], %subreg.ssub
    ; CHECK: [[INSvi32gpr1:%[0-9]+]]:fpr128 = INSvi32gpr [[INSERT_SUBREG1]], 1, [[MOVi32imm1]]
    ; CHECK: [[COPY3:%[0-9]+]]:fpr64 = COPY [[INSvi32gpr1]].dsub
    ; CHECK: [[ANDv8i8_1:%[0-9]+]]:fpr64 = ANDv8i8 [[COPY1]], [[COPY3]]
    ; CHECK: [[CMEQv2i32_:%[0-9]+]]:fpr64 = CMEQv2i32 [[ANDv8i8_]], [[ANDv8i8_1]]
    ; CHECK: [[NOTv8i8_:%[0-9]+]]:fpr64 = NOTv8i8 [[CMEQv2i32_]]
    ; CHECK: $d0 = COPY [[NOTv8i8_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %2:fpr(<2 x s32>) = COPY $d0
    %3:fpr(<2 x s32>) = COPY $d1
    %13:gpr(s32) = G_CONSTANT i32 65535
    %14:fpr(<2 x s32>) = G_BUILD_VECTOR %13(s32), %13(s32)
    %15:fpr(<2 x s32>) = COPY %2(<2 x s32>)
    %7:fpr(<2 x s32>) = G_AND %15, %14
    %10:gpr(s32) = G_CONSTANT i32 65535
    %11:fpr(<2 x s32>) = G_BUILD_VECTOR %10(s32), %10(s32)
    %12:fpr(<2 x s32>) = COPY %3(<2 x s32>)
    %8:fpr(<2 x s32>) = G_AND %12, %11
    %9:fpr(<2 x s32>) = G_ICMP intpred(ne), %7(<2 x s32>), %8
    %5:fpr(<2 x s32>) = COPY %9(<2 x s32>)
    $d0 = COPY %5(<2 x s32>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v8i16_ne
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v8i16_ne
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
    ; CHECK: [[CMEQv8i16_:%[0-9]+]]:fpr128 = CMEQv8i16 [[COPY]], [[COPY1]]
    ; CHECK: [[NOTv16i8_:%[0-9]+]]:fpr128 = NOTv16i8 [[CMEQv8i16_]]
    ; CHECK: [[XTNv8i8_:%[0-9]+]]:fpr64 = XTNv8i8 [[NOTv16i8_]]
    ; CHECK: $d0 = COPY [[XTNv8i8_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %0:fpr(<8 x s16>) = COPY $q0
    %1:fpr(<8 x s16>) = COPY $q1
    %4:fpr(<8 x s16>) = G_ICMP intpred(ne), %0(<8 x s16>), %1
    %3:fpr(<8 x s8>) = G_TRUNC %4(<8 x s16>)
    $d0 = COPY %3(<8 x s8>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v4i16_ne
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $d0, $d1

    ; CHECK-LABEL: name: test_v4i16_ne
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
    ; CHECK: [[CMEQv4i16_:%[0-9]+]]:fpr64 = CMEQv4i16 [[COPY]], [[COPY1]]
    ; CHECK: [[NOTv8i8_:%[0-9]+]]:fpr64 = NOTv8i8 [[CMEQv4i16_]]
    ; CHECK: $d0 = COPY [[NOTv8i8_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %0:fpr(<4 x s16>) = COPY $d0
    %1:fpr(<4 x s16>) = COPY $d1
    %4:fpr(<4 x s16>) = G_ICMP intpred(ne), %0(<4 x s16>), %1
    %3:fpr(<4 x s16>) = COPY %4(<4 x s16>)
    $d0 = COPY %3(<4 x s16>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v16i8_ne
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v16i8_ne
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
    ; CHECK: [[CMEQv16i8_:%[0-9]+]]:fpr128 = CMEQv16i8 [[COPY]], [[COPY1]]
    ; CHECK: [[NOTv16i8_:%[0-9]+]]:fpr128 = NOTv16i8 [[CMEQv16i8_]]
    ; CHECK: $q0 = COPY [[NOTv16i8_]]
    ; CHECK: RET_ReallyLR implicit $q0
    %0:fpr(<16 x s8>) = COPY $q0
    %1:fpr(<16 x s8>) = COPY $q1
    %4:fpr(<16 x s8>) = G_ICMP intpred(ne), %0(<16 x s8>), %1
    %3:fpr(<16 x s8>) = COPY %4(<16 x s8>)
    $q0 = COPY %3(<16 x s8>)
    RET_ReallyLR implicit $q0

...
---
name:            test_v8i8_ne
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $d0, $d1

    ; CHECK-LABEL: name: test_v8i8_ne
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
    ; CHECK: [[CMEQv8i8_:%[0-9]+]]:fpr64 = CMEQv8i8 [[COPY]], [[COPY1]]
    ; CHECK: [[NOTv8i8_:%[0-9]+]]:fpr64 = NOTv8i8 [[CMEQv8i8_]]
    ; CHECK: $d0 = COPY [[NOTv8i8_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %0:fpr(<8 x s8>) = COPY $d0
    %1:fpr(<8 x s8>) = COPY $d1
    %4:fpr(<8 x s8>) = G_ICMP intpred(ne), %0(<8 x s8>), %1
    %3:fpr(<8 x s8>) = COPY %4(<8 x s8>)
    $d0 = COPY %3(<8 x s8>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v2i64_ugt
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v2i64_ugt
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
    ; CHECK: [[CMHIv2i64_:%[0-9]+]]:fpr128 = CMHIv2i64 [[COPY]], [[COPY1]]
    ; CHECK: [[XTNv2i32_:%[0-9]+]]:fpr64 = XTNv2i32 [[CMHIv2i64_]]
    ; CHECK: $d0 = COPY [[XTNv2i32_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %0:fpr(<2 x s64>) = COPY $q0
    %1:fpr(<2 x s64>) = COPY $q1
    %4:fpr(<2 x s64>) = G_ICMP intpred(ugt), %0(<2 x s64>), %1
    %3:fpr(<2 x s32>) = G_TRUNC %4(<2 x s64>)
    $d0 = COPY %3(<2 x s32>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v4i32_ugt
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v4i32_ugt
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
    ; CHECK: [[CMHIv4i32_:%[0-9]+]]:fpr128 = CMHIv4i32 [[COPY]], [[COPY1]]
    ; CHECK: [[XTNv4i16_:%[0-9]+]]:fpr64 = XTNv4i16 [[CMHIv4i32_]]
    ; CHECK: $d0 = COPY [[XTNv4i16_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %0:fpr(<4 x s32>) = COPY $q0
    %1:fpr(<4 x s32>) = COPY $q1
    %4:fpr(<4 x s32>) = G_ICMP intpred(ugt), %0(<4 x s32>), %1
    %3:fpr(<4 x s16>) = G_TRUNC %4(<4 x s32>)
    $d0 = COPY %3(<4 x s16>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v2i32_ugt
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $d0, $d1

    ; CHECK-LABEL: name: test_v2i32_ugt
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
    ; CHECK: [[CMHIv2i32_:%[0-9]+]]:fpr64 = CMHIv2i32 [[COPY]], [[COPY1]]
    ; CHECK: $d0 = COPY [[CMHIv2i32_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %0:fpr(<2 x s32>) = COPY $d0
    %1:fpr(<2 x s32>) = COPY $d1
    %4:fpr(<2 x s32>) = G_ICMP intpred(ugt), %0(<2 x s32>), %1
    %3:fpr(<2 x s32>) = COPY %4(<2 x s32>)
    $d0 = COPY %3(<2 x s32>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v2i16_ugt
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: fpr }
  - { id: 3, class: fpr }
  - { id: 4, class: _ }
  - { id: 5, class: fpr }
  - { id: 6, class: _ }
  - { id: 7, class: fpr }
  - { id: 8, class: fpr }
  - { id: 9, class: fpr }
  - { id: 10, class: gpr }
  - { id: 11, class: fpr }
  - { id: 12, class: fpr }
  - { id: 13, class: gpr }
  - { id: 14, class: fpr }
  - { id: 15, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $d0, $d1

    ; CHECK-LABEL: name: test_v2i16_ugt
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
    ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 65535
    ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[MOVi32imm]], %subreg.ssub
    ; CHECK: [[INSvi32gpr:%[0-9]+]]:fpr128 = INSvi32gpr [[INSERT_SUBREG]], 1, [[MOVi32imm]]
    ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi32gpr]].dsub
    ; CHECK: [[ANDv8i8_:%[0-9]+]]:fpr64 = ANDv8i8 [[COPY]], [[COPY2]]
    ; CHECK: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 65535
    ; CHECK: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
    ; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[MOVi32imm1]], %subreg.ssub
    ; CHECK: [[INSvi32gpr1:%[0-9]+]]:fpr128 = INSvi32gpr [[INSERT_SUBREG1]], 1, [[MOVi32imm1]]
    ; CHECK: [[COPY3:%[0-9]+]]:fpr64 = COPY [[INSvi32gpr1]].dsub
    ; CHECK: [[ANDv8i8_1:%[0-9]+]]:fpr64 = ANDv8i8 [[COPY1]], [[COPY3]]
    ; CHECK: [[CMHIv2i32_:%[0-9]+]]:fpr64 = CMHIv2i32 [[ANDv8i8_]], [[ANDv8i8_1]]
    ; CHECK: $d0 = COPY [[CMHIv2i32_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %2:fpr(<2 x s32>) = COPY $d0
    %3:fpr(<2 x s32>) = COPY $d1
    %13:gpr(s32) = G_CONSTANT i32 65535
    %14:fpr(<2 x s32>) = G_BUILD_VECTOR %13(s32), %13(s32)
    %15:fpr(<2 x s32>) = COPY %2(<2 x s32>)
    %7:fpr(<2 x s32>) = G_AND %15, %14
    %10:gpr(s32) = G_CONSTANT i32 65535
    %11:fpr(<2 x s32>) = G_BUILD_VECTOR %10(s32), %10(s32)
    %12:fpr(<2 x s32>) = COPY %3(<2 x s32>)
    %8:fpr(<2 x s32>) = G_AND %12, %11
    %9:fpr(<2 x s32>) = G_ICMP intpred(ugt), %7(<2 x s32>), %8
    %5:fpr(<2 x s32>) = COPY %9(<2 x s32>)
    $d0 = COPY %5(<2 x s32>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v8i16_ugt
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v8i16_ugt
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
    ; CHECK: [[CMHIv8i16_:%[0-9]+]]:fpr128 = CMHIv8i16 [[COPY]], [[COPY1]]
    ; CHECK: [[XTNv8i8_:%[0-9]+]]:fpr64 = XTNv8i8 [[CMHIv8i16_]]
    ; CHECK: $d0 = COPY [[XTNv8i8_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %0:fpr(<8 x s16>) = COPY $q0
    %1:fpr(<8 x s16>) = COPY $q1
    %4:fpr(<8 x s16>) = G_ICMP intpred(ugt), %0(<8 x s16>), %1
    %3:fpr(<8 x s8>) = G_TRUNC %4(<8 x s16>)
    $d0 = COPY %3(<8 x s8>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v4i16_ugt
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $d0, $d1

    ; CHECK-LABEL: name: test_v4i16_ugt
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
    ; CHECK: [[CMHIv4i16_:%[0-9]+]]:fpr64 = CMHIv4i16 [[COPY]], [[COPY1]]
    ; CHECK: $d0 = COPY [[CMHIv4i16_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %0:fpr(<4 x s16>) = COPY $d0
    %1:fpr(<4 x s16>) = COPY $d1
    %4:fpr(<4 x s16>) = G_ICMP intpred(ugt), %0(<4 x s16>), %1
    %3:fpr(<4 x s16>) = COPY %4(<4 x s16>)
    $d0 = COPY %3(<4 x s16>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v16i8_ugt
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v16i8_ugt
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
    ; CHECK: [[CMHIv16i8_:%[0-9]+]]:fpr128 = CMHIv16i8 [[COPY]], [[COPY1]]
    ; CHECK: $q0 = COPY [[CMHIv16i8_]]
    ; CHECK: RET_ReallyLR implicit $q0
    %0:fpr(<16 x s8>) = COPY $q0
    %1:fpr(<16 x s8>) = COPY $q1
    %4:fpr(<16 x s8>) = G_ICMP intpred(ugt), %0(<16 x s8>), %1
    %3:fpr(<16 x s8>) = COPY %4(<16 x s8>)
    $q0 = COPY %3(<16 x s8>)
    RET_ReallyLR implicit $q0

...
---
name:            test_v8i8_ugt
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $d0, $d1

    ; CHECK-LABEL: name: test_v8i8_ugt
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
    ; CHECK: [[CMHIv8i8_:%[0-9]+]]:fpr64 = CMHIv8i8 [[COPY]], [[COPY1]]
    ; CHECK: $d0 = COPY [[CMHIv8i8_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %0:fpr(<8 x s8>) = COPY $d0
    %1:fpr(<8 x s8>) = COPY $d1
    %4:fpr(<8 x s8>) = G_ICMP intpred(ugt), %0(<8 x s8>), %1
    %3:fpr(<8 x s8>) = COPY %4(<8 x s8>)
    $d0 = COPY %3(<8 x s8>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v2i64_uge
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v2i64_uge
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
    ; CHECK: [[CMHSv2i64_:%[0-9]+]]:fpr128 = CMHSv2i64 [[COPY]], [[COPY1]]
    ; CHECK: [[XTNv2i32_:%[0-9]+]]:fpr64 = XTNv2i32 [[CMHSv2i64_]]
    ; CHECK: $d0 = COPY [[XTNv2i32_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %0:fpr(<2 x s64>) = COPY $q0
    %1:fpr(<2 x s64>) = COPY $q1
    %4:fpr(<2 x s64>) = G_ICMP intpred(uge), %0(<2 x s64>), %1
    %3:fpr(<2 x s32>) = G_TRUNC %4(<2 x s64>)
    $d0 = COPY %3(<2 x s32>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v4i32_uge
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v4i32_uge
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
    ; CHECK: [[CMHSv4i32_:%[0-9]+]]:fpr128 = CMHSv4i32 [[COPY]], [[COPY1]]
    ; CHECK: [[XTNv4i16_:%[0-9]+]]:fpr64 = XTNv4i16 [[CMHSv4i32_]]
    ; CHECK: $d0 = COPY [[XTNv4i16_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %0:fpr(<4 x s32>) = COPY $q0
    %1:fpr(<4 x s32>) = COPY $q1
    %4:fpr(<4 x s32>) = G_ICMP intpred(uge), %0(<4 x s32>), %1
    %3:fpr(<4 x s16>) = G_TRUNC %4(<4 x s32>)
    $d0 = COPY %3(<4 x s16>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v2i32_uge
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $d0, $d1

    ; CHECK-LABEL: name: test_v2i32_uge
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
    ; CHECK: [[CMHSv2i32_:%[0-9]+]]:fpr64 = CMHSv2i32 [[COPY]], [[COPY1]]
    ; CHECK: $d0 = COPY [[CMHSv2i32_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %0:fpr(<2 x s32>) = COPY $d0
    %1:fpr(<2 x s32>) = COPY $d1
    %4:fpr(<2 x s32>) = G_ICMP intpred(uge), %0(<2 x s32>), %1
    %3:fpr(<2 x s32>) = COPY %4(<2 x s32>)
    $d0 = COPY %3(<2 x s32>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v2i16_uge
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: fpr }
  - { id: 3, class: fpr }
  - { id: 4, class: _ }
  - { id: 5, class: fpr }
  - { id: 6, class: _ }
  - { id: 7, class: fpr }
  - { id: 8, class: fpr }
  - { id: 9, class: fpr }
  - { id: 10, class: gpr }
  - { id: 11, class: fpr }
  - { id: 12, class: fpr }
  - { id: 13, class: gpr }
  - { id: 14, class: fpr }
  - { id: 15, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $d0, $d1

    ; CHECK-LABEL: name: test_v2i16_uge
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
    ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 65535
    ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[MOVi32imm]], %subreg.ssub
    ; CHECK: [[INSvi32gpr:%[0-9]+]]:fpr128 = INSvi32gpr [[INSERT_SUBREG]], 1, [[MOVi32imm]]
    ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi32gpr]].dsub
    ; CHECK: [[ANDv8i8_:%[0-9]+]]:fpr64 = ANDv8i8 [[COPY]], [[COPY2]]
    ; CHECK: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 65535
    ; CHECK: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
    ; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[MOVi32imm1]], %subreg.ssub
    ; CHECK: [[INSvi32gpr1:%[0-9]+]]:fpr128 = INSvi32gpr [[INSERT_SUBREG1]], 1, [[MOVi32imm1]]
    ; CHECK: [[COPY3:%[0-9]+]]:fpr64 = COPY [[INSvi32gpr1]].dsub
    ; CHECK: [[ANDv8i8_1:%[0-9]+]]:fpr64 = ANDv8i8 [[COPY1]], [[COPY3]]
    ; CHECK: [[CMHSv2i32_:%[0-9]+]]:fpr64 = CMHSv2i32 [[ANDv8i8_]], [[ANDv8i8_1]]
    ; CHECK: $d0 = COPY [[CMHSv2i32_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %2:fpr(<2 x s32>) = COPY $d0
    %3:fpr(<2 x s32>) = COPY $d1
    %13:gpr(s32) = G_CONSTANT i32 65535
    %14:fpr(<2 x s32>) = G_BUILD_VECTOR %13(s32), %13(s32)
    %15:fpr(<2 x s32>) = COPY %2(<2 x s32>)
    %7:fpr(<2 x s32>) = G_AND %15, %14
    %10:gpr(s32) = G_CONSTANT i32 65535
    %11:fpr(<2 x s32>) = G_BUILD_VECTOR %10(s32), %10(s32)
    %12:fpr(<2 x s32>) = COPY %3(<2 x s32>)
    %8:fpr(<2 x s32>) = G_AND %12, %11
    %9:fpr(<2 x s32>) = G_ICMP intpred(uge), %7(<2 x s32>), %8
    %5:fpr(<2 x s32>) = COPY %9(<2 x s32>)
    $d0 = COPY %5(<2 x s32>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v8i16_uge
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v8i16_uge
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
    ; CHECK: [[CMHSv8i16_:%[0-9]+]]:fpr128 = CMHSv8i16 [[COPY]], [[COPY1]]
    ; CHECK: [[XTNv8i8_:%[0-9]+]]:fpr64 = XTNv8i8 [[CMHSv8i16_]]
    ; CHECK: $d0 = COPY [[XTNv8i8_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %0:fpr(<8 x s16>) = COPY $q0
    %1:fpr(<8 x s16>) = COPY $q1
    %4:fpr(<8 x s16>) = G_ICMP intpred(uge), %0(<8 x s16>), %1
    %3:fpr(<8 x s8>) = G_TRUNC %4(<8 x s16>)
    $d0 = COPY %3(<8 x s8>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v4i16_uge
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $d0, $d1

    ; CHECK-LABEL: name: test_v4i16_uge
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
    ; CHECK: [[CMHSv4i16_:%[0-9]+]]:fpr64 = CMHSv4i16 [[COPY]], [[COPY1]]
    ; CHECK: $d0 = COPY [[CMHSv4i16_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %0:fpr(<4 x s16>) = COPY $d0
    %1:fpr(<4 x s16>) = COPY $d1
    %4:fpr(<4 x s16>) = G_ICMP intpred(uge), %0(<4 x s16>), %1
    %3:fpr(<4 x s16>) = COPY %4(<4 x s16>)
    $d0 = COPY %3(<4 x s16>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v16i8_uge
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v16i8_uge
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
    ; CHECK: [[CMHSv16i8_:%[0-9]+]]:fpr128 = CMHSv16i8 [[COPY]], [[COPY1]]
    ; CHECK: $q0 = COPY [[CMHSv16i8_]]
    ; CHECK: RET_ReallyLR implicit $q0
    %0:fpr(<16 x s8>) = COPY $q0
    %1:fpr(<16 x s8>) = COPY $q1
    %4:fpr(<16 x s8>) = G_ICMP intpred(uge), %0(<16 x s8>), %1
    %3:fpr(<16 x s8>) = COPY %4(<16 x s8>)
    $q0 = COPY %3(<16 x s8>)
    RET_ReallyLR implicit $q0

...
---
name:            test_v8i8_uge
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $d0, $d1

    ; CHECK-LABEL: name: test_v8i8_uge
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
    ; CHECK: [[CMHSv8i8_:%[0-9]+]]:fpr64 = CMHSv8i8 [[COPY]], [[COPY1]]
    ; CHECK: $d0 = COPY [[CMHSv8i8_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %0:fpr(<8 x s8>) = COPY $d0
    %1:fpr(<8 x s8>) = COPY $d1
    %4:fpr(<8 x s8>) = G_ICMP intpred(uge), %0(<8 x s8>), %1
    %3:fpr(<8 x s8>) = COPY %4(<8 x s8>)
    $d0 = COPY %3(<8 x s8>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v2i64_ult
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v2i64_ult
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
    ; CHECK: [[CMHIv2i64_:%[0-9]+]]:fpr128 = CMHIv2i64 [[COPY1]], [[COPY]]
    ; CHECK: [[XTNv2i32_:%[0-9]+]]:fpr64 = XTNv2i32 [[CMHIv2i64_]]
    ; CHECK: $d0 = COPY [[XTNv2i32_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %0:fpr(<2 x s64>) = COPY $q0
    %1:fpr(<2 x s64>) = COPY $q1
    %4:fpr(<2 x s64>) = G_ICMP intpred(ult), %0(<2 x s64>), %1
    %3:fpr(<2 x s32>) = G_TRUNC %4(<2 x s64>)
    $d0 = COPY %3(<2 x s32>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v4i32_ult
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v4i32_ult
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
    ; CHECK: [[CMHIv4i32_:%[0-9]+]]:fpr128 = CMHIv4i32 [[COPY1]], [[COPY]]
    ; CHECK: [[XTNv4i16_:%[0-9]+]]:fpr64 = XTNv4i16 [[CMHIv4i32_]]
    ; CHECK: $d0 = COPY [[XTNv4i16_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %0:fpr(<4 x s32>) = COPY $q0
    %1:fpr(<4 x s32>) = COPY $q1
    %4:fpr(<4 x s32>) = G_ICMP intpred(ult), %0(<4 x s32>), %1
    %3:fpr(<4 x s16>) = G_TRUNC %4(<4 x s32>)
    $d0 = COPY %3(<4 x s16>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v2i32_ult
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $d0, $d1

    ; CHECK-LABEL: name: test_v2i32_ult
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
    ; CHECK: [[CMHIv2i32_:%[0-9]+]]:fpr64 = CMHIv2i32 [[COPY1]], [[COPY]]
    ; CHECK: $d0 = COPY [[CMHIv2i32_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %0:fpr(<2 x s32>) = COPY $d0
    %1:fpr(<2 x s32>) = COPY $d1
    %4:fpr(<2 x s32>) = G_ICMP intpred(ult), %0(<2 x s32>), %1
    %3:fpr(<2 x s32>) = COPY %4(<2 x s32>)
    $d0 = COPY %3(<2 x s32>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v2i16_ult
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: fpr }
  - { id: 3, class: fpr }
  - { id: 4, class: _ }
  - { id: 5, class: fpr }
  - { id: 6, class: _ }
  - { id: 7, class: fpr }
  - { id: 8, class: fpr }
  - { id: 9, class: fpr }
  - { id: 10, class: gpr }
  - { id: 11, class: fpr }
  - { id: 12, class: fpr }
  - { id: 13, class: gpr }
  - { id: 14, class: fpr }
  - { id: 15, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $d0, $d1

    ; CHECK-LABEL: name: test_v2i16_ult
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
    ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 65535
    ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[MOVi32imm]], %subreg.ssub
    ; CHECK: [[INSvi32gpr:%[0-9]+]]:fpr128 = INSvi32gpr [[INSERT_SUBREG]], 1, [[MOVi32imm]]
    ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi32gpr]].dsub
    ; CHECK: [[ANDv8i8_:%[0-9]+]]:fpr64 = ANDv8i8 [[COPY]], [[COPY2]]
    ; CHECK: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 65535
    ; CHECK: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
    ; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[MOVi32imm1]], %subreg.ssub
    ; CHECK: [[INSvi32gpr1:%[0-9]+]]:fpr128 = INSvi32gpr [[INSERT_SUBREG1]], 1, [[MOVi32imm1]]
    ; CHECK: [[COPY3:%[0-9]+]]:fpr64 = COPY [[INSvi32gpr1]].dsub
    ; CHECK: [[ANDv8i8_1:%[0-9]+]]:fpr64 = ANDv8i8 [[COPY1]], [[COPY3]]
    ; CHECK: [[CMHIv2i32_:%[0-9]+]]:fpr64 = CMHIv2i32 [[ANDv8i8_1]], [[ANDv8i8_]]
    ; CHECK: $d0 = COPY [[CMHIv2i32_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %2:fpr(<2 x s32>) = COPY $d0
    %3:fpr(<2 x s32>) = COPY $d1
    %13:gpr(s32) = G_CONSTANT i32 65535
    %14:fpr(<2 x s32>) = G_BUILD_VECTOR %13(s32), %13(s32)
    %15:fpr(<2 x s32>) = COPY %2(<2 x s32>)
    %7:fpr(<2 x s32>) = G_AND %15, %14
    %10:gpr(s32) = G_CONSTANT i32 65535
    %11:fpr(<2 x s32>) = G_BUILD_VECTOR %10(s32), %10(s32)
    %12:fpr(<2 x s32>) = COPY %3(<2 x s32>)
    %8:fpr(<2 x s32>) = G_AND %12, %11
    %9:fpr(<2 x s32>) = G_ICMP intpred(ult), %7(<2 x s32>), %8
    %5:fpr(<2 x s32>) = COPY %9(<2 x s32>)
    $d0 = COPY %5(<2 x s32>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v8i16_ult
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v8i16_ult
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
    ; CHECK: [[CMHIv8i16_:%[0-9]+]]:fpr128 = CMHIv8i16 [[COPY1]], [[COPY]]
    ; CHECK: [[XTNv8i8_:%[0-9]+]]:fpr64 = XTNv8i8 [[CMHIv8i16_]]
    ; CHECK: $d0 = COPY [[XTNv8i8_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %0:fpr(<8 x s16>) = COPY $q0
    %1:fpr(<8 x s16>) = COPY $q1
    %4:fpr(<8 x s16>) = G_ICMP intpred(ult), %0(<8 x s16>), %1
    %3:fpr(<8 x s8>) = G_TRUNC %4(<8 x s16>)
    $d0 = COPY %3(<8 x s8>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v4i16_ult
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $d0, $d1

    ; CHECK-LABEL: name: test_v4i16_ult
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
    ; CHECK: [[CMHIv4i16_:%[0-9]+]]:fpr64 = CMHIv4i16 [[COPY1]], [[COPY]]
    ; CHECK: $d0 = COPY [[CMHIv4i16_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %0:fpr(<4 x s16>) = COPY $d0
    %1:fpr(<4 x s16>) = COPY $d1
    %4:fpr(<4 x s16>) = G_ICMP intpred(ult), %0(<4 x s16>), %1
    %3:fpr(<4 x s16>) = COPY %4(<4 x s16>)
    $d0 = COPY %3(<4 x s16>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v16i8_ult
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v16i8_ult
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
    ; CHECK: [[CMHIv16i8_:%[0-9]+]]:fpr128 = CMHIv16i8 [[COPY1]], [[COPY]]
    ; CHECK: $q0 = COPY [[CMHIv16i8_]]
    ; CHECK: RET_ReallyLR implicit $q0
    %0:fpr(<16 x s8>) = COPY $q0
    %1:fpr(<16 x s8>) = COPY $q1
    %4:fpr(<16 x s8>) = G_ICMP intpred(ult), %0(<16 x s8>), %1
    %3:fpr(<16 x s8>) = COPY %4(<16 x s8>)
    $q0 = COPY %3(<16 x s8>)
    RET_ReallyLR implicit $q0

...
---
name:            test_v8i8_ult
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $d0, $d1

    ; CHECK-LABEL: name: test_v8i8_ult
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
    ; CHECK: [[CMHIv8i8_:%[0-9]+]]:fpr64 = CMHIv8i8 [[COPY1]], [[COPY]]
    ; CHECK: $d0 = COPY [[CMHIv8i8_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %0:fpr(<8 x s8>) = COPY $d0
    %1:fpr(<8 x s8>) = COPY $d1
    %4:fpr(<8 x s8>) = G_ICMP intpred(ult), %0(<8 x s8>), %1
    %3:fpr(<8 x s8>) = COPY %4(<8 x s8>)
    $d0 = COPY %3(<8 x s8>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v2i64_ule
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v2i64_ule
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
    ; CHECK: [[CMHSv2i64_:%[0-9]+]]:fpr128 = CMHSv2i64 [[COPY1]], [[COPY]]
    ; CHECK: [[XTNv2i32_:%[0-9]+]]:fpr64 = XTNv2i32 [[CMHSv2i64_]]
    ; CHECK: $d0 = COPY [[XTNv2i32_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %0:fpr(<2 x s64>) = COPY $q0
    %1:fpr(<2 x s64>) = COPY $q1
    %4:fpr(<2 x s64>) = G_ICMP intpred(ule), %0(<2 x s64>), %1
    %3:fpr(<2 x s32>) = G_TRUNC %4(<2 x s64>)
    $d0 = COPY %3(<2 x s32>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v4i32_ule
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v4i32_ule
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
    ; CHECK: [[CMHSv4i32_:%[0-9]+]]:fpr128 = CMHSv4i32 [[COPY1]], [[COPY]]
    ; CHECK: [[XTNv4i16_:%[0-9]+]]:fpr64 = XTNv4i16 [[CMHSv4i32_]]
    ; CHECK: $d0 = COPY [[XTNv4i16_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %0:fpr(<4 x s32>) = COPY $q0
    %1:fpr(<4 x s32>) = COPY $q1
    %4:fpr(<4 x s32>) = G_ICMP intpred(ule), %0(<4 x s32>), %1
    %3:fpr(<4 x s16>) = G_TRUNC %4(<4 x s32>)
    $d0 = COPY %3(<4 x s16>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v2i32_ule
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $d0, $d1

    ; CHECK-LABEL: name: test_v2i32_ule
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
    ; CHECK: [[CMHSv2i32_:%[0-9]+]]:fpr64 = CMHSv2i32 [[COPY1]], [[COPY]]
    ; CHECK: $d0 = COPY [[CMHSv2i32_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %0:fpr(<2 x s32>) = COPY $d0
    %1:fpr(<2 x s32>) = COPY $d1
    %4:fpr(<2 x s32>) = G_ICMP intpred(ule), %0(<2 x s32>), %1
    %3:fpr(<2 x s32>) = COPY %4(<2 x s32>)
    $d0 = COPY %3(<2 x s32>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v2i16_ule
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: fpr }
  - { id: 3, class: fpr }
  - { id: 4, class: _ }
  - { id: 5, class: fpr }
  - { id: 6, class: _ }
  - { id: 7, class: fpr }
  - { id: 8, class: fpr }
  - { id: 9, class: fpr }
  - { id: 10, class: gpr }
  - { id: 11, class: fpr }
  - { id: 12, class: fpr }
  - { id: 13, class: gpr }
  - { id: 14, class: fpr }
  - { id: 15, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $d0, $d1

    ; CHECK-LABEL: name: test_v2i16_ule
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
    ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 65535
    ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[MOVi32imm]], %subreg.ssub
    ; CHECK: [[INSvi32gpr:%[0-9]+]]:fpr128 = INSvi32gpr [[INSERT_SUBREG]], 1, [[MOVi32imm]]
    ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi32gpr]].dsub
    ; CHECK: [[ANDv8i8_:%[0-9]+]]:fpr64 = ANDv8i8 [[COPY]], [[COPY2]]
    ; CHECK: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 65535
    ; CHECK: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
    ; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[MOVi32imm1]], %subreg.ssub
    ; CHECK: [[INSvi32gpr1:%[0-9]+]]:fpr128 = INSvi32gpr [[INSERT_SUBREG1]], 1, [[MOVi32imm1]]
    ; CHECK: [[COPY3:%[0-9]+]]:fpr64 = COPY [[INSvi32gpr1]].dsub
    ; CHECK: [[ANDv8i8_1:%[0-9]+]]:fpr64 = ANDv8i8 [[COPY1]], [[COPY3]]
    ; CHECK: [[CMHSv2i32_:%[0-9]+]]:fpr64 = CMHSv2i32 [[ANDv8i8_1]], [[ANDv8i8_]]
    ; CHECK: $d0 = COPY [[CMHSv2i32_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %2:fpr(<2 x s32>) = COPY $d0
    %3:fpr(<2 x s32>) = COPY $d1
    %13:gpr(s32) = G_CONSTANT i32 65535
    %14:fpr(<2 x s32>) = G_BUILD_VECTOR %13(s32), %13(s32)
    %15:fpr(<2 x s32>) = COPY %2(<2 x s32>)
    %7:fpr(<2 x s32>) = G_AND %15, %14
    %10:gpr(s32) = G_CONSTANT i32 65535
    %11:fpr(<2 x s32>) = G_BUILD_VECTOR %10(s32), %10(s32)
    %12:fpr(<2 x s32>) = COPY %3(<2 x s32>)
    %8:fpr(<2 x s32>) = G_AND %12, %11
    %9:fpr(<2 x s32>) = G_ICMP intpred(ule), %7(<2 x s32>), %8
    %5:fpr(<2 x s32>) = COPY %9(<2 x s32>)
    $d0 = COPY %5(<2 x s32>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v8i16_ule
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v8i16_ule
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
    ; CHECK: [[CMHSv8i16_:%[0-9]+]]:fpr128 = CMHSv8i16 [[COPY1]], [[COPY]]
    ; CHECK: [[XTNv8i8_:%[0-9]+]]:fpr64 = XTNv8i8 [[CMHSv8i16_]]
    ; CHECK: $d0 = COPY [[XTNv8i8_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %0:fpr(<8 x s16>) = COPY $q0
    %1:fpr(<8 x s16>) = COPY $q1
    %4:fpr(<8 x s16>) = G_ICMP intpred(ule), %0(<8 x s16>), %1
    %3:fpr(<8 x s8>) = G_TRUNC %4(<8 x s16>)
    $d0 = COPY %3(<8 x s8>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v4i16_ule
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $d0, $d1

    ; CHECK-LABEL: name: test_v4i16_ule
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
    ; CHECK: [[CMHSv4i16_:%[0-9]+]]:fpr64 = CMHSv4i16 [[COPY1]], [[COPY]]
    ; CHECK: $d0 = COPY [[CMHSv4i16_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %0:fpr(<4 x s16>) = COPY $d0
    %1:fpr(<4 x s16>) = COPY $d1
    %4:fpr(<4 x s16>) = G_ICMP intpred(ule), %0(<4 x s16>), %1
    %3:fpr(<4 x s16>) = COPY %4(<4 x s16>)
    $d0 = COPY %3(<4 x s16>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v16i8_ule
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v16i8_ule
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
    ; CHECK: [[CMHSv16i8_:%[0-9]+]]:fpr128 = CMHSv16i8 [[COPY1]], [[COPY]]
    ; CHECK: $q0 = COPY [[CMHSv16i8_]]
    ; CHECK: RET_ReallyLR implicit $q0
    %0:fpr(<16 x s8>) = COPY $q0
    %1:fpr(<16 x s8>) = COPY $q1
    %4:fpr(<16 x s8>) = G_ICMP intpred(ule), %0(<16 x s8>), %1
    %3:fpr(<16 x s8>) = COPY %4(<16 x s8>)
    $q0 = COPY %3(<16 x s8>)
    RET_ReallyLR implicit $q0

...
---
name:            test_v8i8_ule
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $d0, $d1

    ; CHECK-LABEL: name: test_v8i8_ule
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
    ; CHECK: [[CMHSv8i8_:%[0-9]+]]:fpr64 = CMHSv8i8 [[COPY1]], [[COPY]]
    ; CHECK: $d0 = COPY [[CMHSv8i8_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %0:fpr(<8 x s8>) = COPY $d0
    %1:fpr(<8 x s8>) = COPY $d1
    %4:fpr(<8 x s8>) = G_ICMP intpred(ule), %0(<8 x s8>), %1
    %3:fpr(<8 x s8>) = COPY %4(<8 x s8>)
    $d0 = COPY %3(<8 x s8>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v2i64_sgt
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v2i64_sgt
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
    ; CHECK: [[CMGTv2i64_:%[0-9]+]]:fpr128 = CMGTv2i64 [[COPY]], [[COPY1]]
    ; CHECK: [[XTNv2i32_:%[0-9]+]]:fpr64 = XTNv2i32 [[CMGTv2i64_]]
    ; CHECK: $d0 = COPY [[XTNv2i32_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %0:fpr(<2 x s64>) = COPY $q0
    %1:fpr(<2 x s64>) = COPY $q1
    %4:fpr(<2 x s64>) = G_ICMP intpred(sgt), %0(<2 x s64>), %1
    %3:fpr(<2 x s32>) = G_TRUNC %4(<2 x s64>)
    $d0 = COPY %3(<2 x s32>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v4i32_sgt
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v4i32_sgt
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
    ; CHECK: [[CMGTv4i32_:%[0-9]+]]:fpr128 = CMGTv4i32 [[COPY]], [[COPY1]]
    ; CHECK: [[XTNv4i16_:%[0-9]+]]:fpr64 = XTNv4i16 [[CMGTv4i32_]]
    ; CHECK: $d0 = COPY [[XTNv4i16_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %0:fpr(<4 x s32>) = COPY $q0
    %1:fpr(<4 x s32>) = COPY $q1
    %4:fpr(<4 x s32>) = G_ICMP intpred(sgt), %0(<4 x s32>), %1
    %3:fpr(<4 x s16>) = G_TRUNC %4(<4 x s32>)
    $d0 = COPY %3(<4 x s16>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v2i32_sgt
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $d0, $d1

    ; CHECK-LABEL: name: test_v2i32_sgt
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
    ; CHECK: [[CMGTv2i32_:%[0-9]+]]:fpr64 = CMGTv2i32 [[COPY]], [[COPY1]]
    ; CHECK: $d0 = COPY [[CMGTv2i32_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %0:fpr(<2 x s32>) = COPY $d0
    %1:fpr(<2 x s32>) = COPY $d1
    %4:fpr(<2 x s32>) = G_ICMP intpred(sgt), %0(<2 x s32>), %1
    %3:fpr(<2 x s32>) = COPY %4(<2 x s32>)
    $d0 = COPY %3(<2 x s32>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v2i16_sgt
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: fpr }
  - { id: 3, class: fpr }
  - { id: 4, class: _ }
  - { id: 5, class: fpr }
  - { id: 6, class: _ }
  - { id: 7, class: fpr }
  - { id: 8, class: fpr }
  - { id: 9, class: fpr }
  - { id: 10, class: gpr }
  - { id: 11, class: fpr }
  - { id: 12, class: fpr }
  - { id: 13, class: fpr }
  - { id: 14, class: gpr }
  - { id: 15, class: fpr }
  - { id: 16, class: fpr }
  - { id: 17, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $d0, $d1

    ; CHECK-LABEL: name: test_v2i16_sgt
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
    ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 16
    ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[MOVi32imm]], %subreg.ssub
    ; CHECK: [[INSvi32gpr:%[0-9]+]]:fpr128 = INSvi32gpr [[INSERT_SUBREG]], 1, [[MOVi32imm]]
    ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi32gpr]].dsub
    ; CHECK: [[USHLv2i32_:%[0-9]+]]:fpr64 = USHLv2i32 [[COPY]], [[COPY2]]
    ; CHECK: [[NEGv2i32_:%[0-9]+]]:fpr64 = NEGv2i32 [[COPY2]]
    ; CHECK: [[SSHLv2i32_:%[0-9]+]]:fpr64 = SSHLv2i32 [[USHLv2i32_]], [[NEGv2i32_]]
    ; CHECK: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 16
    ; CHECK: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
    ; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[MOVi32imm1]], %subreg.ssub
    ; CHECK: [[INSvi32gpr1:%[0-9]+]]:fpr128 = INSvi32gpr [[INSERT_SUBREG1]], 1, [[MOVi32imm1]]
    ; CHECK: [[COPY3:%[0-9]+]]:fpr64 = COPY [[INSvi32gpr1]].dsub
    ; CHECK: [[USHLv2i32_1:%[0-9]+]]:fpr64 = USHLv2i32 [[COPY1]], [[COPY3]]
    ; CHECK: [[NEGv2i32_1:%[0-9]+]]:fpr64 = NEGv2i32 [[COPY3]]
    ; CHECK: [[SSHLv2i32_1:%[0-9]+]]:fpr64 = SSHLv2i32 [[USHLv2i32_1]], [[NEGv2i32_1]]
    ; CHECK: [[CMGTv2i32_:%[0-9]+]]:fpr64 = CMGTv2i32 [[SSHLv2i32_]], [[SSHLv2i32_1]]
    ; CHECK: $d0 = COPY [[CMGTv2i32_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %2:fpr(<2 x s32>) = COPY $d0
    %3:fpr(<2 x s32>) = COPY $d1
    %14:gpr(s32) = G_CONSTANT i32 16
    %15:fpr(<2 x s32>) = G_BUILD_VECTOR %14(s32), %14(s32)
    %16:fpr(<2 x s32>) = COPY %2(<2 x s32>)
    %17:fpr(<2 x s32>) = G_SHL %16, %15(<2 x s32>)
    %7:fpr(<2 x s32>) = G_ASHR %17, %15(<2 x s32>)
    %10:gpr(s32) = G_CONSTANT i32 16
    %11:fpr(<2 x s32>) = G_BUILD_VECTOR %10(s32), %10(s32)
    %12:fpr(<2 x s32>) = COPY %3(<2 x s32>)
    %13:fpr(<2 x s32>) = G_SHL %12, %11(<2 x s32>)
    %8:fpr(<2 x s32>) = G_ASHR %13, %11(<2 x s32>)
    %9:fpr(<2 x s32>) = G_ICMP intpred(sgt), %7(<2 x s32>), %8
    %5:fpr(<2 x s32>) = COPY %9(<2 x s32>)
    $d0 = COPY %5(<2 x s32>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v8i16_sgt
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v8i16_sgt
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
    ; CHECK: [[CMGTv8i16_:%[0-9]+]]:fpr128 = CMGTv8i16 [[COPY]], [[COPY1]]
    ; CHECK: [[XTNv8i8_:%[0-9]+]]:fpr64 = XTNv8i8 [[CMGTv8i16_]]
    ; CHECK: $d0 = COPY [[XTNv8i8_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %0:fpr(<8 x s16>) = COPY $q0
    %1:fpr(<8 x s16>) = COPY $q1
    %4:fpr(<8 x s16>) = G_ICMP intpred(sgt), %0(<8 x s16>), %1
    %3:fpr(<8 x s8>) = G_TRUNC %4(<8 x s16>)
    $d0 = COPY %3(<8 x s8>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v4i16_sgt
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $d0, $d1

    ; CHECK-LABEL: name: test_v4i16_sgt
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
    ; CHECK: [[CMGTv4i16_:%[0-9]+]]:fpr64 = CMGTv4i16 [[COPY]], [[COPY1]]
    ; CHECK: $d0 = COPY [[CMGTv4i16_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %0:fpr(<4 x s16>) = COPY $d0
    %1:fpr(<4 x s16>) = COPY $d1
    %4:fpr(<4 x s16>) = G_ICMP intpred(sgt), %0(<4 x s16>), %1
    %3:fpr(<4 x s16>) = COPY %4(<4 x s16>)
    $d0 = COPY %3(<4 x s16>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v16i8_sgt
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v16i8_sgt
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
    ; CHECK: [[CMGTv16i8_:%[0-9]+]]:fpr128 = CMGTv16i8 [[COPY]], [[COPY1]]
    ; CHECK: $q0 = COPY [[CMGTv16i8_]]
    ; CHECK: RET_ReallyLR implicit $q0
    %0:fpr(<16 x s8>) = COPY $q0
    %1:fpr(<16 x s8>) = COPY $q1
    %4:fpr(<16 x s8>) = G_ICMP intpred(sgt), %0(<16 x s8>), %1
    %3:fpr(<16 x s8>) = COPY %4(<16 x s8>)
    $q0 = COPY %3(<16 x s8>)
    RET_ReallyLR implicit $q0

...
---
name:            test_v8i8_sgt
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $d0, $d1

    ; CHECK-LABEL: name: test_v8i8_sgt
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
    ; CHECK: [[CMGTv8i8_:%[0-9]+]]:fpr64 = CMGTv8i8 [[COPY]], [[COPY1]]
    ; CHECK: $d0 = COPY [[CMGTv8i8_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %0:fpr(<8 x s8>) = COPY $d0
    %1:fpr(<8 x s8>) = COPY $d1
    %4:fpr(<8 x s8>) = G_ICMP intpred(sgt), %0(<8 x s8>), %1
    %3:fpr(<8 x s8>) = COPY %4(<8 x s8>)
    $d0 = COPY %3(<8 x s8>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v2i64_sge
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v2i64_sge
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
    ; CHECK: [[CMGEv2i64_:%[0-9]+]]:fpr128 = CMGEv2i64 [[COPY]], [[COPY1]]
    ; CHECK: [[XTNv2i32_:%[0-9]+]]:fpr64 = XTNv2i32 [[CMGEv2i64_]]
    ; CHECK: $d0 = COPY [[XTNv2i32_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %0:fpr(<2 x s64>) = COPY $q0
    %1:fpr(<2 x s64>) = COPY $q1
    %4:fpr(<2 x s64>) = G_ICMP intpred(sge), %0(<2 x s64>), %1
    %3:fpr(<2 x s32>) = G_TRUNC %4(<2 x s64>)
    $d0 = COPY %3(<2 x s32>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v4i32_sge
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v4i32_sge
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
    ; CHECK: [[CMGEv4i32_:%[0-9]+]]:fpr128 = CMGEv4i32 [[COPY]], [[COPY1]]
    ; CHECK: [[XTNv4i16_:%[0-9]+]]:fpr64 = XTNv4i16 [[CMGEv4i32_]]
    ; CHECK: $d0 = COPY [[XTNv4i16_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %0:fpr(<4 x s32>) = COPY $q0
    %1:fpr(<4 x s32>) = COPY $q1
    %4:fpr(<4 x s32>) = G_ICMP intpred(sge), %0(<4 x s32>), %1
    %3:fpr(<4 x s16>) = G_TRUNC %4(<4 x s32>)
    $d0 = COPY %3(<4 x s16>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v2i32_sge
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $d0, $d1

    ; CHECK-LABEL: name: test_v2i32_sge
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
    ; CHECK: [[CMGEv2i32_:%[0-9]+]]:fpr64 = CMGEv2i32 [[COPY]], [[COPY1]]
    ; CHECK: $d0 = COPY [[CMGEv2i32_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %0:fpr(<2 x s32>) = COPY $d0
    %1:fpr(<2 x s32>) = COPY $d1
    %4:fpr(<2 x s32>) = G_ICMP intpred(sge), %0(<2 x s32>), %1
    %3:fpr(<2 x s32>) = COPY %4(<2 x s32>)
    $d0 = COPY %3(<2 x s32>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v2i16_sge
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: fpr }
  - { id: 3, class: fpr }
  - { id: 4, class: _ }
  - { id: 5, class: fpr }
  - { id: 6, class: _ }
  - { id: 7, class: fpr }
  - { id: 8, class: fpr }
  - { id: 9, class: fpr }
  - { id: 10, class: gpr }
  - { id: 11, class: fpr }
  - { id: 12, class: fpr }
  - { id: 13, class: fpr }
  - { id: 14, class: gpr }
  - { id: 15, class: fpr }
  - { id: 16, class: fpr }
  - { id: 17, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $d0, $d1

    ; CHECK-LABEL: name: test_v2i16_sge
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
    ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 16
    ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[MOVi32imm]], %subreg.ssub
    ; CHECK: [[INSvi32gpr:%[0-9]+]]:fpr128 = INSvi32gpr [[INSERT_SUBREG]], 1, [[MOVi32imm]]
    ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi32gpr]].dsub
    ; CHECK: [[USHLv2i32_:%[0-9]+]]:fpr64 = USHLv2i32 [[COPY]], [[COPY2]]
    ; CHECK: [[NEGv2i32_:%[0-9]+]]:fpr64 = NEGv2i32 [[COPY2]]
    ; CHECK: [[SSHLv2i32_:%[0-9]+]]:fpr64 = SSHLv2i32 [[USHLv2i32_]], [[NEGv2i32_]]
    ; CHECK: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 16
    ; CHECK: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
    ; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[MOVi32imm1]], %subreg.ssub
    ; CHECK: [[INSvi32gpr1:%[0-9]+]]:fpr128 = INSvi32gpr [[INSERT_SUBREG1]], 1, [[MOVi32imm1]]
    ; CHECK: [[COPY3:%[0-9]+]]:fpr64 = COPY [[INSvi32gpr1]].dsub
    ; CHECK: [[USHLv2i32_1:%[0-9]+]]:fpr64 = USHLv2i32 [[COPY1]], [[COPY3]]
    ; CHECK: [[NEGv2i32_1:%[0-9]+]]:fpr64 = NEGv2i32 [[COPY3]]
    ; CHECK: [[SSHLv2i32_1:%[0-9]+]]:fpr64 = SSHLv2i32 [[USHLv2i32_1]], [[NEGv2i32_1]]
    ; CHECK: [[CMGEv2i32_:%[0-9]+]]:fpr64 = CMGEv2i32 [[SSHLv2i32_]], [[SSHLv2i32_1]]
    ; CHECK: $d0 = COPY [[CMGEv2i32_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %2:fpr(<2 x s32>) = COPY $d0
    %3:fpr(<2 x s32>) = COPY $d1
    %14:gpr(s32) = G_CONSTANT i32 16
    %15:fpr(<2 x s32>) = G_BUILD_VECTOR %14(s32), %14(s32)
    %16:fpr(<2 x s32>) = COPY %2(<2 x s32>)
    %17:fpr(<2 x s32>) = G_SHL %16, %15(<2 x s32>)
    %7:fpr(<2 x s32>) = G_ASHR %17, %15(<2 x s32>)
    %10:gpr(s32) = G_CONSTANT i32 16
    %11:fpr(<2 x s32>) = G_BUILD_VECTOR %10(s32), %10(s32)
    %12:fpr(<2 x s32>) = COPY %3(<2 x s32>)
    %13:fpr(<2 x s32>) = G_SHL %12, %11(<2 x s32>)
    %8:fpr(<2 x s32>) = G_ASHR %13, %11(<2 x s32>)
    %9:fpr(<2 x s32>) = G_ICMP intpred(sge), %7(<2 x s32>), %8
    %5:fpr(<2 x s32>) = COPY %9(<2 x s32>)
    $d0 = COPY %5(<2 x s32>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v8i16_sge
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v8i16_sge
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
    ; CHECK: [[CMGEv8i16_:%[0-9]+]]:fpr128 = CMGEv8i16 [[COPY]], [[COPY1]]
    ; CHECK: [[XTNv8i8_:%[0-9]+]]:fpr64 = XTNv8i8 [[CMGEv8i16_]]
    ; CHECK: $d0 = COPY [[XTNv8i8_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %0:fpr(<8 x s16>) = COPY $q0
    %1:fpr(<8 x s16>) = COPY $q1
    %4:fpr(<8 x s16>) = G_ICMP intpred(sge), %0(<8 x s16>), %1
    %3:fpr(<8 x s8>) = G_TRUNC %4(<8 x s16>)
    $d0 = COPY %3(<8 x s8>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v4i16_sge
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $d0, $d1

    ; CHECK-LABEL: name: test_v4i16_sge
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
    ; CHECK: [[CMGEv4i16_:%[0-9]+]]:fpr64 = CMGEv4i16 [[COPY]], [[COPY1]]
    ; CHECK: $d0 = COPY [[CMGEv4i16_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %0:fpr(<4 x s16>) = COPY $d0
    %1:fpr(<4 x s16>) = COPY $d1
    %4:fpr(<4 x s16>) = G_ICMP intpred(sge), %0(<4 x s16>), %1
    %3:fpr(<4 x s16>) = COPY %4(<4 x s16>)
    $d0 = COPY %3(<4 x s16>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v16i8_sge
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v16i8_sge
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
    ; CHECK: [[CMGEv16i8_:%[0-9]+]]:fpr128 = CMGEv16i8 [[COPY]], [[COPY1]]
    ; CHECK: $q0 = COPY [[CMGEv16i8_]]
    ; CHECK: RET_ReallyLR implicit $q0
    %0:fpr(<16 x s8>) = COPY $q0
    %1:fpr(<16 x s8>) = COPY $q1
    %4:fpr(<16 x s8>) = G_ICMP intpred(sge), %0(<16 x s8>), %1
    %3:fpr(<16 x s8>) = COPY %4(<16 x s8>)
    $q0 = COPY %3(<16 x s8>)
    RET_ReallyLR implicit $q0

...
---
name:            test_v8i8_sge
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $d0, $d1

    ; CHECK-LABEL: name: test_v8i8_sge
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
    ; CHECK: [[CMGEv8i8_:%[0-9]+]]:fpr64 = CMGEv8i8 [[COPY]], [[COPY1]]
    ; CHECK: $d0 = COPY [[CMGEv8i8_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %0:fpr(<8 x s8>) = COPY $d0
    %1:fpr(<8 x s8>) = COPY $d1
    %4:fpr(<8 x s8>) = G_ICMP intpred(sge), %0(<8 x s8>), %1
    %3:fpr(<8 x s8>) = COPY %4(<8 x s8>)
    $d0 = COPY %3(<8 x s8>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v2i64_slt
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v2i64_slt
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
    ; CHECK: [[CMGTv2i64_:%[0-9]+]]:fpr128 = CMGTv2i64 [[COPY1]], [[COPY]]
    ; CHECK: [[XTNv2i32_:%[0-9]+]]:fpr64 = XTNv2i32 [[CMGTv2i64_]]
    ; CHECK: $d0 = COPY [[XTNv2i32_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %0:fpr(<2 x s64>) = COPY $q0
    %1:fpr(<2 x s64>) = COPY $q1
    %4:fpr(<2 x s64>) = G_ICMP intpred(slt), %0(<2 x s64>), %1
    %3:fpr(<2 x s32>) = G_TRUNC %4(<2 x s64>)
    $d0 = COPY %3(<2 x s32>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v4i32_slt
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v4i32_slt
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
    ; CHECK: [[CMGTv4i32_:%[0-9]+]]:fpr128 = CMGTv4i32 [[COPY1]], [[COPY]]
    ; CHECK: [[XTNv4i16_:%[0-9]+]]:fpr64 = XTNv4i16 [[CMGTv4i32_]]
    ; CHECK: $d0 = COPY [[XTNv4i16_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %0:fpr(<4 x s32>) = COPY $q0
    %1:fpr(<4 x s32>) = COPY $q1
    %4:fpr(<4 x s32>) = G_ICMP intpred(slt), %0(<4 x s32>), %1
    %3:fpr(<4 x s16>) = G_TRUNC %4(<4 x s32>)
    $d0 = COPY %3(<4 x s16>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v2i32_slt
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $d0, $d1

    ; CHECK-LABEL: name: test_v2i32_slt
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
    ; CHECK: [[CMGTv2i32_:%[0-9]+]]:fpr64 = CMGTv2i32 [[COPY1]], [[COPY]]
    ; CHECK: $d0 = COPY [[CMGTv2i32_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %0:fpr(<2 x s32>) = COPY $d0
    %1:fpr(<2 x s32>) = COPY $d1
    %4:fpr(<2 x s32>) = G_ICMP intpred(slt), %0(<2 x s32>), %1
    %3:fpr(<2 x s32>) = COPY %4(<2 x s32>)
    $d0 = COPY %3(<2 x s32>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v2i16_slt
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: fpr }
  - { id: 3, class: fpr }
  - { id: 4, class: _ }
  - { id: 5, class: fpr }
  - { id: 6, class: _ }
  - { id: 7, class: fpr }
  - { id: 8, class: fpr }
  - { id: 9, class: fpr }
  - { id: 10, class: gpr }
  - { id: 11, class: fpr }
  - { id: 12, class: fpr }
  - { id: 13, class: fpr }
  - { id: 14, class: gpr }
  - { id: 15, class: fpr }
  - { id: 16, class: fpr }
  - { id: 17, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $d0, $d1

    ; CHECK-LABEL: name: test_v2i16_slt
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
    ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 16
    ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[MOVi32imm]], %subreg.ssub
    ; CHECK: [[INSvi32gpr:%[0-9]+]]:fpr128 = INSvi32gpr [[INSERT_SUBREG]], 1, [[MOVi32imm]]
    ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi32gpr]].dsub
    ; CHECK: [[USHLv2i32_:%[0-9]+]]:fpr64 = USHLv2i32 [[COPY]], [[COPY2]]
    ; CHECK: [[NEGv2i32_:%[0-9]+]]:fpr64 = NEGv2i32 [[COPY2]]
    ; CHECK: [[SSHLv2i32_:%[0-9]+]]:fpr64 = SSHLv2i32 [[USHLv2i32_]], [[NEGv2i32_]]
    ; CHECK: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 16
    ; CHECK: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
    ; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[MOVi32imm1]], %subreg.ssub
    ; CHECK: [[INSvi32gpr1:%[0-9]+]]:fpr128 = INSvi32gpr [[INSERT_SUBREG1]], 1, [[MOVi32imm1]]
    ; CHECK: [[COPY3:%[0-9]+]]:fpr64 = COPY [[INSvi32gpr1]].dsub
    ; CHECK: [[USHLv2i32_1:%[0-9]+]]:fpr64 = USHLv2i32 [[COPY1]], [[COPY3]]
    ; CHECK: [[NEGv2i32_1:%[0-9]+]]:fpr64 = NEGv2i32 [[COPY3]]
    ; CHECK: [[SSHLv2i32_1:%[0-9]+]]:fpr64 = SSHLv2i32 [[USHLv2i32_1]], [[NEGv2i32_1]]
    ; CHECK: [[CMGTv2i32_:%[0-9]+]]:fpr64 = CMGTv2i32 [[SSHLv2i32_1]], [[SSHLv2i32_]]
    ; CHECK: $d0 = COPY [[CMGTv2i32_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %2:fpr(<2 x s32>) = COPY $d0
    %3:fpr(<2 x s32>) = COPY $d1
    %14:gpr(s32) = G_CONSTANT i32 16
    %15:fpr(<2 x s32>) = G_BUILD_VECTOR %14(s32), %14(s32)
    %16:fpr(<2 x s32>) = COPY %2(<2 x s32>)
    %17:fpr(<2 x s32>) = G_SHL %16, %15(<2 x s32>)
    %7:fpr(<2 x s32>) = G_ASHR %17, %15(<2 x s32>)
    %10:gpr(s32) = G_CONSTANT i32 16
    %11:fpr(<2 x s32>) = G_BUILD_VECTOR %10(s32), %10(s32)
    %12:fpr(<2 x s32>) = COPY %3(<2 x s32>)
    %13:fpr(<2 x s32>) = G_SHL %12, %11(<2 x s32>)
    %8:fpr(<2 x s32>) = G_ASHR %13, %11(<2 x s32>)
    %9:fpr(<2 x s32>) = G_ICMP intpred(slt), %7(<2 x s32>), %8
    %5:fpr(<2 x s32>) = COPY %9(<2 x s32>)
    $d0 = COPY %5(<2 x s32>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v8i16_slt
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v8i16_slt
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
    ; CHECK: [[CMGTv8i16_:%[0-9]+]]:fpr128 = CMGTv8i16 [[COPY1]], [[COPY]]
    ; CHECK: [[XTNv8i8_:%[0-9]+]]:fpr64 = XTNv8i8 [[CMGTv8i16_]]
    ; CHECK: $d0 = COPY [[XTNv8i8_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %0:fpr(<8 x s16>) = COPY $q0
    %1:fpr(<8 x s16>) = COPY $q1
    %4:fpr(<8 x s16>) = G_ICMP intpred(slt), %0(<8 x s16>), %1
    %3:fpr(<8 x s8>) = G_TRUNC %4(<8 x s16>)
    $d0 = COPY %3(<8 x s8>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v4i16_slt
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $d0, $d1

    ; CHECK-LABEL: name: test_v4i16_slt
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
    ; CHECK: [[CMGTv4i16_:%[0-9]+]]:fpr64 = CMGTv4i16 [[COPY1]], [[COPY]]
    ; CHECK: $d0 = COPY [[CMGTv4i16_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %0:fpr(<4 x s16>) = COPY $d0
    %1:fpr(<4 x s16>) = COPY $d1
    %4:fpr(<4 x s16>) = G_ICMP intpred(slt), %0(<4 x s16>), %1
    %3:fpr(<4 x s16>) = COPY %4(<4 x s16>)
    $d0 = COPY %3(<4 x s16>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v16i8_slt
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v16i8_slt
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
    ; CHECK: [[CMGTv16i8_:%[0-9]+]]:fpr128 = CMGTv16i8 [[COPY1]], [[COPY]]
    ; CHECK: $q0 = COPY [[CMGTv16i8_]]
    ; CHECK: RET_ReallyLR implicit $q0
    %0:fpr(<16 x s8>) = COPY $q0
    %1:fpr(<16 x s8>) = COPY $q1
    %4:fpr(<16 x s8>) = G_ICMP intpred(slt), %0(<16 x s8>), %1
    %3:fpr(<16 x s8>) = COPY %4(<16 x s8>)
    $q0 = COPY %3(<16 x s8>)
    RET_ReallyLR implicit $q0

...
---
name:            test_v8i8_slt
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $d0, $d1

    ; CHECK-LABEL: name: test_v8i8_slt
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
    ; CHECK: [[CMGTv8i8_:%[0-9]+]]:fpr64 = CMGTv8i8 [[COPY1]], [[COPY]]
    ; CHECK: $d0 = COPY [[CMGTv8i8_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %0:fpr(<8 x s8>) = COPY $d0
    %1:fpr(<8 x s8>) = COPY $d1
    %4:fpr(<8 x s8>) = G_ICMP intpred(slt), %0(<8 x s8>), %1
    %3:fpr(<8 x s8>) = COPY %4(<8 x s8>)
    $d0 = COPY %3(<8 x s8>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v2i64_sle
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v2i64_sle
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
    ; CHECK: [[CMGEv2i64_:%[0-9]+]]:fpr128 = CMGEv2i64 [[COPY1]], [[COPY]]
    ; CHECK: [[XTNv2i32_:%[0-9]+]]:fpr64 = XTNv2i32 [[CMGEv2i64_]]
    ; CHECK: $d0 = COPY [[XTNv2i32_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %0:fpr(<2 x s64>) = COPY $q0
    %1:fpr(<2 x s64>) = COPY $q1
    %4:fpr(<2 x s64>) = G_ICMP intpred(sle), %0(<2 x s64>), %1
    %3:fpr(<2 x s32>) = G_TRUNC %4(<2 x s64>)
    $d0 = COPY %3(<2 x s32>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v4i32_sle
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v4i32_sle
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
    ; CHECK: [[CMGEv4i32_:%[0-9]+]]:fpr128 = CMGEv4i32 [[COPY1]], [[COPY]]
    ; CHECK: [[XTNv4i16_:%[0-9]+]]:fpr64 = XTNv4i16 [[CMGEv4i32_]]
    ; CHECK: $d0 = COPY [[XTNv4i16_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %0:fpr(<4 x s32>) = COPY $q0
    %1:fpr(<4 x s32>) = COPY $q1
    %4:fpr(<4 x s32>) = G_ICMP intpred(sle), %0(<4 x s32>), %1
    %3:fpr(<4 x s16>) = G_TRUNC %4(<4 x s32>)
    $d0 = COPY %3(<4 x s16>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v2i32_sle
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $d0, $d1

    ; CHECK-LABEL: name: test_v2i32_sle
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
    ; CHECK: [[CMGEv2i32_:%[0-9]+]]:fpr64 = CMGEv2i32 [[COPY1]], [[COPY]]
    ; CHECK: $d0 = COPY [[CMGEv2i32_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %0:fpr(<2 x s32>) = COPY $d0
    %1:fpr(<2 x s32>) = COPY $d1
    %4:fpr(<2 x s32>) = G_ICMP intpred(sle), %0(<2 x s32>), %1
    %3:fpr(<2 x s32>) = COPY %4(<2 x s32>)
    $d0 = COPY %3(<2 x s32>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v2i16_sle
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: fpr }
  - { id: 3, class: fpr }
  - { id: 4, class: _ }
  - { id: 5, class: fpr }
  - { id: 6, class: _ }
  - { id: 7, class: fpr }
  - { id: 8, class: fpr }
  - { id: 9, class: fpr }
  - { id: 10, class: gpr }
  - { id: 11, class: fpr }
  - { id: 12, class: fpr }
  - { id: 13, class: fpr }
  - { id: 14, class: gpr }
  - { id: 15, class: fpr }
  - { id: 16, class: fpr }
  - { id: 17, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $d0, $d1

    ; CHECK-LABEL: name: test_v2i16_sle
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
    ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 16
    ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[MOVi32imm]], %subreg.ssub
    ; CHECK: [[INSvi32gpr:%[0-9]+]]:fpr128 = INSvi32gpr [[INSERT_SUBREG]], 1, [[MOVi32imm]]
    ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi32gpr]].dsub
    ; CHECK: [[USHLv2i32_:%[0-9]+]]:fpr64 = USHLv2i32 [[COPY]], [[COPY2]]
    ; CHECK: [[NEGv2i32_:%[0-9]+]]:fpr64 = NEGv2i32 [[COPY2]]
    ; CHECK: [[SSHLv2i32_:%[0-9]+]]:fpr64 = SSHLv2i32 [[USHLv2i32_]], [[NEGv2i32_]]
    ; CHECK: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 16
    ; CHECK: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
    ; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[MOVi32imm1]], %subreg.ssub
    ; CHECK: [[INSvi32gpr1:%[0-9]+]]:fpr128 = INSvi32gpr [[INSERT_SUBREG1]], 1, [[MOVi32imm1]]
    ; CHECK: [[COPY3:%[0-9]+]]:fpr64 = COPY [[INSvi32gpr1]].dsub
    ; CHECK: [[USHLv2i32_1:%[0-9]+]]:fpr64 = USHLv2i32 [[COPY1]], [[COPY3]]
    ; CHECK: [[NEGv2i32_1:%[0-9]+]]:fpr64 = NEGv2i32 [[COPY3]]
    ; CHECK: [[SSHLv2i32_1:%[0-9]+]]:fpr64 = SSHLv2i32 [[USHLv2i32_1]], [[NEGv2i32_1]]
    ; CHECK: [[CMGEv2i32_:%[0-9]+]]:fpr64 = CMGEv2i32 [[SSHLv2i32_1]], [[SSHLv2i32_]]
    ; CHECK: $d0 = COPY [[CMGEv2i32_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %2:fpr(<2 x s32>) = COPY $d0
    %3:fpr(<2 x s32>) = COPY $d1
    %14:gpr(s32) = G_CONSTANT i32 16
    %15:fpr(<2 x s32>) = G_BUILD_VECTOR %14(s32), %14(s32)
    %16:fpr(<2 x s32>) = COPY %2(<2 x s32>)
    %17:fpr(<2 x s32>) = G_SHL %16, %15(<2 x s32>)
    %7:fpr(<2 x s32>) = G_ASHR %17, %15(<2 x s32>)
    %10:gpr(s32) = G_CONSTANT i32 16
    %11:fpr(<2 x s32>) = G_BUILD_VECTOR %10(s32), %10(s32)
    %12:fpr(<2 x s32>) = COPY %3(<2 x s32>)
    %13:fpr(<2 x s32>) = G_SHL %12, %11(<2 x s32>)
    %8:fpr(<2 x s32>) = G_ASHR %13, %11(<2 x s32>)
    %9:fpr(<2 x s32>) = G_ICMP intpred(sle), %7(<2 x s32>), %8
    %5:fpr(<2 x s32>) = COPY %9(<2 x s32>)
    $d0 = COPY %5(<2 x s32>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v8i16_sle
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v8i16_sle
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
    ; CHECK: [[CMGEv8i16_:%[0-9]+]]:fpr128 = CMGEv8i16 [[COPY1]], [[COPY]]
    ; CHECK: [[XTNv8i8_:%[0-9]+]]:fpr64 = XTNv8i8 [[CMGEv8i16_]]
    ; CHECK: $d0 = COPY [[XTNv8i8_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %0:fpr(<8 x s16>) = COPY $q0
    %1:fpr(<8 x s16>) = COPY $q1
    %4:fpr(<8 x s16>) = G_ICMP intpred(sle), %0(<8 x s16>), %1
    %3:fpr(<8 x s8>) = G_TRUNC %4(<8 x s16>)
    $d0 = COPY %3(<8 x s8>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v4i16_sle
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $d0, $d1

    ; CHECK-LABEL: name: test_v4i16_sle
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
    ; CHECK: [[CMGEv4i16_:%[0-9]+]]:fpr64 = CMGEv4i16 [[COPY1]], [[COPY]]
    ; CHECK: $d0 = COPY [[CMGEv4i16_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %0:fpr(<4 x s16>) = COPY $d0
    %1:fpr(<4 x s16>) = COPY $d1
    %4:fpr(<4 x s16>) = G_ICMP intpred(sle), %0(<4 x s16>), %1
    %3:fpr(<4 x s16>) = COPY %4(<4 x s16>)
    $d0 = COPY %3(<4 x s16>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v16i8_sle
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v16i8_sle
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
    ; CHECK: [[CMGEv16i8_:%[0-9]+]]:fpr128 = CMGEv16i8 [[COPY1]], [[COPY]]
    ; CHECK: $q0 = COPY [[CMGEv16i8_]]
    ; CHECK: RET_ReallyLR implicit $q0
    %0:fpr(<16 x s8>) = COPY $q0
    %1:fpr(<16 x s8>) = COPY $q1
    %4:fpr(<16 x s8>) = G_ICMP intpred(sle), %0(<16 x s8>), %1
    %3:fpr(<16 x s8>) = COPY %4(<16 x s8>)
    $q0 = COPY %3(<16 x s8>)
    RET_ReallyLR implicit $q0

...
---
name:            test_v8i8_sle
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: _ }
  - { id: 3, class: fpr }
  - { id: 4, class: fpr }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $d0, $d1

    ; CHECK-LABEL: name: test_v8i8_sle
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
    ; CHECK: [[CMGEv8i8_:%[0-9]+]]:fpr64 = CMGEv8i8 [[COPY1]], [[COPY]]
    ; CHECK: $d0 = COPY [[CMGEv8i8_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %0:fpr(<8 x s8>) = COPY $d0
    %1:fpr(<8 x s8>) = COPY $d1
    %4:fpr(<8 x s8>) = G_ICMP intpred(sle), %0(<8 x s8>), %1
    %3:fpr(<8 x s8>) = COPY %4(<8 x s8>)
    $d0 = COPY %3(<8 x s8>)
    RET_ReallyLR implicit $d0

...