test/CodeGen/AArch64/GlobalISel/select-redundant-zext-of-load.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64-- -O0 -run-pass=instruction-select -verify-machineinstrs %s -global-isel-abort=1 -o - | FileCheck %s
---
name:            redundant_zext_8
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $x0

    ; CHECK-LABEL: name: redundant_zext_8
    ; CHECK: liveins: $x0
    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
    ; CHECK: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load 1)
    ; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRBBui]]
    ; CHECK: $w0 = COPY [[COPY1]]
    ; CHECK: RET_ReallyLR implicit $w0
    %1:gpr(p0) = COPY $x0
    %2:gpr(s8) = G_LOAD %1(p0) :: (load 1)
    %3:gpr(s32) = G_ZEXT %2(s8)
    $w0 = COPY %3(s32)
    RET_ReallyLR implicit $w0

...
---
name:            redundant_zext_16
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $x0

    ; CHECK-LABEL: name: redundant_zext_16
    ; CHECK: liveins: $x0
    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
    ; CHECK: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load 2)
    ; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRHHui]]
    ; CHECK: $w0 = COPY [[COPY1]]
    ; CHECK: RET_ReallyLR implicit $w0
    %1:gpr(p0) = COPY $x0
    %2:gpr(s16) = G_LOAD %1(p0) :: (load 2)
    %3:gpr(s32) = G_ZEXT %2(s16)
    $w0 = COPY %3(s32)
    RET_ReallyLR implicit $w0

...