test/CodeGen/AArch64/GlobalISel/select-logical-imm.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64-unknown-unknown -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s

---
name:            logical_imm_64_and
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $x0
    ; CHECK-LABEL: name: logical_imm_64_and
    ; CHECK: liveins: $x0
    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
    ; CHECK: [[ANDXri:%[0-9]+]]:gpr64sp = ANDXri [[COPY]], 4096
    ; CHECK: $x0 = COPY [[ANDXri]]
    ; CHECK: RET_ReallyLR implicit $x0
    %0:gpr(s64) = COPY $x0
    %1:gpr(s64) = G_CONSTANT i64 1
    %2:gpr(s64) = G_AND %0, %1:gpr(s64)
    $x0 = COPY %2:gpr(s64)
    RET_ReallyLR implicit $x0
...
---
name:            logical_imm_64_or
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $x0
    ; CHECK-LABEL: name: logical_imm_64_or
    ; CHECK: liveins: $x0
    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
    ; CHECK: [[ORRXri:%[0-9]+]]:gpr64sp = ORRXri [[COPY]], 4096
    ; CHECK: $x0 = COPY [[ORRXri]]
    ; CHECK: RET_ReallyLR implicit $x0
    %0:gpr(s64) = COPY $x0
    %1:gpr(s64) = G_CONSTANT i64 1
    %2:gpr(s64) = G_OR %0, %1:gpr(s64)
    $x0 = COPY %2:gpr(s64)
    RET_ReallyLR implicit $x0
...
---
name:            logical_imm_64_xor
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $x0
    ; CHECK-LABEL: name: logical_imm_64_xor
    ; CHECK: liveins: $x0
    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
    ; CHECK: [[EORXri:%[0-9]+]]:gpr64sp = EORXri [[COPY]], 4096
    ; CHECK: $x0 = COPY [[EORXri]]
    ; CHECK: RET_ReallyLR implicit $x0
    %0:gpr(s64) = COPY $x0
    %1:gpr(s64) = G_CONSTANT i64 1
    %2:gpr(s64) = G_XOR %0, %1:gpr(s64)
    $x0 = COPY %2:gpr(s64)
    RET_ReallyLR implicit $x0
...
---
name:            logical_imm_32_and
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $w0
    ; CHECK-LABEL: name: logical_imm_32_and
    ; CHECK: liveins: $w0
    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
    ; CHECK: [[ANDWri:%[0-9]+]]:gpr32sp = ANDWri [[COPY]], 0
    ; CHECK: $w0 = COPY [[ANDWri]]
    ; CHECK: RET_ReallyLR implicit $w0
    %0:gpr(s32) = COPY $w0
    %1:gpr(s32) = G_CONSTANT i32 1
    %2:gpr(s32) = G_AND %0, %1:gpr(s32)
    $w0 = COPY %2:gpr(s32)
    RET_ReallyLR implicit $w0
...
---
name:            logical_imm_32_or
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $w0
    ; CHECK-LABEL: name: logical_imm_32_or
    ; CHECK: liveins: $w0
    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
    ; CHECK: [[ORRWri:%[0-9]+]]:gpr32sp = ORRWri [[COPY]], 0
    ; CHECK: $w0 = COPY [[ORRWri]]
    ; CHECK: RET_ReallyLR implicit $w0
    %0:gpr(s32) = COPY $w0
    %1:gpr(s32) = G_CONSTANT i32 1
    %2:gpr(s32) = G_OR %0, %1:gpr(s32)
    $w0 = COPY %2:gpr(s32)
    RET_ReallyLR implicit $w0
...
---
name:            logical_imm_32_xor
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $w0
    ; CHECK-LABEL: name: logical_imm_32_xor
    ; CHECK: liveins: $w0
    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
    ; CHECK: [[EORWri:%[0-9]+]]:gpr32sp = EORWri [[COPY]], 0
    ; CHECK: $w0 = COPY [[EORWri]]
    ; CHECK: RET_ReallyLR implicit $w0
    %0:gpr(s32) = COPY $w0
    %1:gpr(s32) = G_CONSTANT i32 1
    %2:gpr(s32) = G_XOR %0, %1:gpr(s32)
    $w0 = COPY %2:gpr(s32)
    RET_ReallyLR implicit $w0
...