test/CodeGen/AArch64/GlobalISel/select-ldxr-intrin.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64-unknown-unknown -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s

--- |
  define void @test_load_i8(i8* %addr) { ret void }
  define void @test_load_i16(i16* %addr) { ret void }
  define void @test_load_i32(i32* %addr) { ret void }
  define void @test_load_i64(i64* %addr) { ret void }
...
---
name:            test_load_i8
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $x0
    ; CHECK-LABEL: name: test_load_i8
    ; CHECK: liveins: $x0
    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
    ; CHECK: [[LDXRB:%[0-9]+]]:gpr32 = LDXRB [[COPY]] :: (volatile load 1 from %ir.addr)
    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[LDXRB]], %subreg.sub_32
    ; CHECK: $x1 = COPY [[SUBREG_TO_REG]]
    ; CHECK: RET_ReallyLR implicit $x1
    %0:gpr(p0) = COPY $x0
    %1:gpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.ldxr), %0(p0) :: (volatile load 1 from %ir.addr)
    $x1 = COPY %1(s64)
    RET_ReallyLR implicit $x1

...
---
name:            test_load_i16
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $x0
    ; CHECK-LABEL: name: test_load_i16
    ; CHECK: liveins: $x0
    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
    ; CHECK: [[LDXRH:%[0-9]+]]:gpr32 = LDXRH [[COPY]] :: (volatile load 2 from %ir.addr)
    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[LDXRH]], %subreg.sub_32
    ; CHECK: $x1 = COPY [[SUBREG_TO_REG]]
    ; CHECK: RET_ReallyLR implicit $x1
    %0:gpr(p0) = COPY $x0
    %1:gpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.ldxr), %0(p0) :: (volatile load 2 from %ir.addr)
    $x1 = COPY %1(s64)
    RET_ReallyLR implicit $x1

...
---
name:            test_load_i32
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $x0
    ; CHECK-LABEL: name: test_load_i32
    ; CHECK: liveins: $x0
    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
    ; CHECK: [[LDXRW:%[0-9]+]]:gpr32 = LDXRW [[COPY]] :: (volatile load 4 from %ir.addr)
    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[LDXRW]], %subreg.sub_32
    ; CHECK: $x1 = COPY [[SUBREG_TO_REG]]
    ; CHECK: RET_ReallyLR implicit $x1
    %0:gpr(p0) = COPY $x0
    %1:gpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.ldxr), %0(p0) :: (volatile load 4 from %ir.addr)
    $x1 = COPY %1(s64)
    RET_ReallyLR implicit $x1


...
---
name:            test_load_i64
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $x0
    ; CHECK-LABEL: name: test_load_i64
    ; CHECK: liveins: $x0
    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
    ; CHECK: [[LDXRX:%[0-9]+]]:gpr64 = LDXRX [[COPY]] :: (volatile load 8 from %ir.addr)
    ; CHECK: $x1 = COPY [[LDXRX]]
    ; CHECK: RET_ReallyLR implicit $x1
    %0:gpr(p0) = COPY $x0
    %1:gpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.ldxr), %0(p0) :: (volatile load 8 from %ir.addr)
    $x1 = COPY %1(s64)
    RET_ReallyLR implicit $x1