test/CodeGen/AArch64/GlobalISel/select-constant.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s

--- |
  target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"

  define i8 @const_s8() { ret i8 42 }
  define i16 @const_s16() { ret i16 42 }
  define i32 @const_s32() { ret i32 42 }
  define i64 @const_s64() { ret i64 1234567890123 }

  define i32 @fconst_s32() { ret i32 42 }
  define i64 @fconst_s64() { ret i64 1234567890123 }
  define float @fconst_s32_0() { ret float 0.0 }
  define double @fconst_s64_0() { ret double 0.0 }

  define void @optnone_i64() optnone noinline { ret void }
  define void @opt_i64() { ret void }
...

---
name:            const_s8
legalized:       true
regBankSelected: true
body:             |
  bb.0:
    ; CHECK-LABEL: name: const_s8
    ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 42
    ; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY [[MOVi32imm]]
    ; CHECK: $w0 = COPY [[COPY]]
    %0:gpr(s8) = G_CONSTANT i8 42
    %1:gpr(s32) = G_ANYEXT %0(s8)
    $w0 = COPY %1(s32)
...

---
name:            const_s16
legalized:       true
regBankSelected: true
body:             |
  bb.0:
    ; CHECK-LABEL: name: const_s16
    ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 42
    ; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY [[MOVi32imm]]
    ; CHECK: $w0 = COPY [[COPY]]
    %0:gpr(s16) = G_CONSTANT i16 42
    %1:gpr(s32) = G_ANYEXT %0(s16)
    $w0 = COPY %1(s32)
...

---
name:            const_s32
legalized:       true
regBankSelected: true
registers:
  - { id: 0, class: gpr }

body:             |
  bb.0:
    ; CHECK-LABEL: name: const_s32
    ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 42
    ; CHECK: $w0 = COPY [[MOVi32imm]]
    %0(s32) = G_CONSTANT i32 42
    $w0 = COPY %0(s32)
...

---
name:            const_s64
legalized:       true
regBankSelected: true
registers:
  - { id: 0, class: gpr }

body:             |
  bb.0:
    ; CHECK-LABEL: name: const_s64
    ; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm 1234567890123
    ; CHECK: $x0 = COPY [[MOVi64imm]]
    %0(s64) = G_CONSTANT i64 1234567890123
    $x0 = COPY %0(s64)
...

---
name:            fconst_s32
legalized:       true
regBankSelected: true
registers:
  - { id: 0, class: fpr }

body:             |
  bb.0:
    ; CHECK-LABEL: name: fconst_s32
    ; CHECK: [[FMOVSi:%[0-9]+]]:fpr32 = FMOVSi 12
    ; CHECK: $s0 = COPY [[FMOVSi]]
    %0(s32) = G_FCONSTANT float 3.5
    $s0 = COPY %0(s32)
...

---
name:            fconst_s64
legalized:       true
regBankSelected: true
registers:
  - { id: 0, class: fpr }

body:             |
  bb.0:
    ; CHECK-LABEL: name: fconst_s64
    ; CHECK: [[FMOVDi:%[0-9]+]]:fpr64 = FMOVDi 112
    ; CHECK: $d0 = COPY [[FMOVDi]]
    %0(s64) = G_FCONSTANT double 1.0
    $d0 = COPY %0(s64)
...

---
name:            fconst_s32_0
legalized:       true
regBankSelected: true
registers:
  - { id: 0, class: fpr }

body:             |
  bb.0:
    ; CHECK-LABEL: name: fconst_s32_0
    ; CHECK: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
    ; CHECK: $s0 = COPY [[FMOVS0_]]
    %0(s32) = G_FCONSTANT float 0.0
    $s0 = COPY %0(s32)
...

---
name:            fconst_s64_0
legalized:       true
regBankSelected: true
registers:
  - { id: 0, class: fpr }

body:             |
  bb.0:
    ; CHECK-LABEL: name: fconst_s64_0
    ; CHECK: [[FMOVD0_:%[0-9]+]]:fpr64 = FMOVD0
    ; CHECK: $x0 = COPY [[FMOVD0_]]
    %0(s64) = G_FCONSTANT double 0.0
    $x0 = COPY %0(s64)
...
---
name:            optnone_i64
legalized:       true
regBankSelected: true
body: |
  bb.0:
    ; CHECK-LABEL: name: optnone_i64
    ; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm 42
    ; CHECK: $x0 = COPY [[MOVi64imm]]
    ; CHECK: RET_ReallyLR implicit $x0
    %0:gpr(s64) = G_CONSTANT i64 42
    $x0 = COPY %0(s64)
    RET_ReallyLR implicit $x0
...
---
name:            opt_i64
legalized:       true
regBankSelected: true
body: |
  bb.0:
    ; CHECK-LABEL: name: opt_i64
    ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 42
    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
    ; CHECK: $x0 = COPY [[SUBREG_TO_REG]]
    ; CHECK: RET_ReallyLR implicit $x0
    %0:gpr(s64) = G_CONSTANT i64 42
    $x0 = COPY %0(s64)
    RET_ReallyLR implicit $x0
...