test/CodeGen/AArch64/GlobalISel/legalize-dyn-alloca.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=arm64-unknown-unknown -global-isel -global-isel-abort=1 -O0 -run-pass=legalizer %s -o - | FileCheck %s
--- |
  target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
  target triple = "aarch64"

  define i8* @test_simple_alloca(i32 %numelts) {
    %addr = alloca i8, i32 %numelts
    ret i8* %addr
  }

  define i8* @test_aligned_alloca(i32 %numelts) {
    %addr = alloca i8, i32 %numelts, align 32
    ret i8* %addr
  }

  define i128* @test_natural_alloca(i32 %numelts) {
    %addr = alloca i128, i32 %numelts
    ret i128* %addr
  }

...
---
name:            test_simple_alloca
alignment:       4
tracksRegLiveness: true
liveins:
  - { reg: '$w0' }
frameInfo:
  maxAlignment:    1
stack:
  - { id: 0, name: addr, type: variable-sized, alignment: 1 }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $w0

    ; CHECK-LABEL: name: test_simple_alloca
    ; CHECK: liveins: $w0
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
    ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
    ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s32)
    ; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ZEXT]], [[C]]
    ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 15
    ; CHECK: [[ADD:%[0-9]+]]:_(s64) = nuw G_ADD [[MUL]], [[C1]]
    ; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -16
    ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[ADD]], [[C2]]
    ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $sp
    ; CHECK: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY1]](p0)
    ; CHECK: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[PTRTOINT]], [[AND]]
    ; CHECK: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[SUB]](s64)
    ; CHECK: $sp = COPY [[INTTOPTR]](p0)
    ; CHECK: [[COPY2:%[0-9]+]]:_(p0) = COPY [[INTTOPTR]](p0)
    ; CHECK: $x0 = COPY [[COPY2]](p0)
    ; CHECK: RET_ReallyLR implicit $x0
    %0:_(s32) = COPY $w0
    %3:_(s64) = G_CONSTANT i64 1
    %1:_(s64) = G_ZEXT %0(s32)
    %2:_(s64) = G_MUL %1, %3
    %4:_(s64) = G_CONSTANT i64 15
    %5:_(s64) = nuw G_ADD %2, %4
    %6:_(s64) = G_CONSTANT i64 -16
    %7:_(s64) = G_AND %5, %6
    %8:_(p0) = G_DYN_STACKALLOC %7(s64), 0
    $x0 = COPY %8(p0)
    RET_ReallyLR implicit $x0

...
---
name:            test_aligned_alloca
alignment:       4
tracksRegLiveness: true
liveins:
  - { reg: '$w0' }
frameInfo:
  maxAlignment:    32
stack:
  - { id: 0, name: addr, type: variable-sized, alignment: 32 }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $w0

    ; CHECK-LABEL: name: test_aligned_alloca
    ; CHECK: liveins: $w0
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
    ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
    ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s32)
    ; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ZEXT]], [[C]]
    ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 15
    ; CHECK: [[ADD:%[0-9]+]]:_(s64) = nuw G_ADD [[MUL]], [[C1]]
    ; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -16
    ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[ADD]], [[C2]]
    ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $sp
    ; CHECK: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY1]](p0)
    ; CHECK: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[PTRTOINT]], [[AND]]
    ; CHECK: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -32
    ; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C3]]
    ; CHECK: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[AND1]](s64)
    ; CHECK: $sp = COPY [[INTTOPTR]](p0)
    ; CHECK: [[COPY2:%[0-9]+]]:_(p0) = COPY [[INTTOPTR]](p0)
    ; CHECK: $x0 = COPY [[COPY2]](p0)
    ; CHECK: RET_ReallyLR implicit $x0
    %0:_(s32) = COPY $w0
    %3:_(s64) = G_CONSTANT i64 1
    %1:_(s64) = G_ZEXT %0(s32)
    %2:_(s64) = G_MUL %1, %3
    %4:_(s64) = G_CONSTANT i64 15
    %5:_(s64) = nuw G_ADD %2, %4
    %6:_(s64) = G_CONSTANT i64 -16
    %7:_(s64) = G_AND %5, %6
    %8:_(p0) = G_DYN_STACKALLOC %7(s64), 32
    $x0 = COPY %8(p0)
    RET_ReallyLR implicit $x0

...
---
name:            test_natural_alloca
alignment:       4
tracksRegLiveness: true
liveins:
  - { reg: '$w0' }
frameInfo:
  maxAlignment:    1
stack:
  - { id: 0, name: addr, type: variable-sized, alignment: 1 }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $w0

    ; CHECK-LABEL: name: test_natural_alloca
    ; CHECK: liveins: $w0
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
    ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
    ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s32)
    ; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ZEXT]], [[C]]
    ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 15
    ; CHECK: [[ADD:%[0-9]+]]:_(s64) = nuw G_ADD [[MUL]], [[C1]]
    ; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -16
    ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[ADD]], [[C2]]
    ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $sp
    ; CHECK: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY1]](p0)
    ; CHECK: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[PTRTOINT]], [[AND]]
    ; CHECK: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[SUB]](s64)
    ; CHECK: $sp = COPY [[INTTOPTR]](p0)
    ; CHECK: [[COPY2:%[0-9]+]]:_(p0) = COPY [[INTTOPTR]](p0)
    ; CHECK: $x0 = COPY [[COPY2]](p0)
    ; CHECK: RET_ReallyLR implicit $x0
    %0:_(s32) = COPY $w0
    %3:_(s64) = G_CONSTANT i64 16
    %1:_(s64) = G_ZEXT %0(s32)
    %2:_(s64) = G_MUL %1, %3
    %4:_(s64) = G_CONSTANT i64 15
    %5:_(s64) = nuw G_ADD %2, %4
    %6:_(s64) = G_CONSTANT i64 -16
    %7:_(s64) = G_AND %5, %6
    %8:_(p0) = G_DYN_STACKALLOC %7(s64), 0
    $x0 = COPY %8(p0)
    RET_ReallyLR implicit $x0

...