test/CodeGen/AArch64/GlobalISel/legalize-concat-vectors.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64-linux-gnu -O0 -run-pass=legalizer %s -global-isel-abort=1 -o - | FileCheck %s

---
name:            legal_v4s32_v2s32
body: |
  bb.0:
    liveins: $d0, $d1
    ; CHECK-LABEL: name: legal_v4s32_v2s32
    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
    ; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s32>) = G_CONCAT_VECTORS [[COPY]](<2 x s32>), [[COPY1]](<2 x s32>)
    ; CHECK: $q0 = COPY [[CONCAT_VECTORS]](<4 x s32>)
    ; CHECK: RET_ReallyLR
    %0:_(<2 x s32>) = COPY $d0
    %1:_(<2 x s32>) = COPY $d1
    %2:_(<4 x s32>) = G_CONCAT_VECTORS %0(<2 x s32>), %1(<2 x s32>)
    $q0 = COPY %2(<4 x s32>)
    RET_ReallyLR
...
---
name:            legal_v8s16_v4s16
body: |
  bb.0:
    liveins: $d0, $d1
    ; CHECK-LABEL: name: legal_v8s16_v4s16
    ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1
    ; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[COPY]](<4 x s16>), [[COPY1]](<4 x s16>)
    ; CHECK: $q0 = COPY [[CONCAT_VECTORS]](<8 x s16>)
    ; CHECK: RET_ReallyLR
    %0:_(<4 x s16>) = COPY $d0
    %1:_(<4 x s16>) = COPY $d1
    %2:_(<8 x s16>) = G_CONCAT_VECTORS %0(<4 x s16>), %1(<4 x s16>)
    $q0 = COPY %2(<8 x s16>)
    RET_ReallyLR
...