blob: 448f254aa88c06efb4e55b368373ac6d45126296 [file] [log] [blame]
<
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=powerpc64le-linux-gnu < %s | FileCheck %s -check-prefix=PPC64LE
define i8 @test0(i8* %ptr) {
; PPC64LE-LABEL: test0:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lbz 3, 0(3)
; PPC64LE-NEXT: blr
%val = load atomic i8, i8* %ptr unordered, align 1
ret i8 %val
}
define i8 @test1(i8* %ptr) {
; PPC64LE-LABEL: test1:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lbz 3, 0(3)
; PPC64LE-NEXT: blr
%val = load atomic i8, i8* %ptr monotonic, align 1
ret i8 %val
}
define i8 @test2(i8* %ptr) {
; PPC64LE-LABEL: test2:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lbz 3, 0(3)
; PPC64LE-NEXT: cmpd 7, 3, 3
; PPC64LE-NEXT: bne- 7, .+4
; PPC64LE-NEXT: isync
; PPC64LE-NEXT: blr
%val = load atomic i8, i8* %ptr acquire, align 1
ret i8 %val
}
define i8 @test3(i8* %ptr) {
; PPC64LE-LABEL: test3:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: lbz 3, 0(3)
; PPC64LE-NEXT: cmpd 7, 3, 3
; PPC64LE-NEXT: bne- 7, .+4
; PPC64LE-NEXT: isync
; PPC64LE-NEXT: blr
%val = load atomic i8, i8* %ptr seq_cst, align 1
ret i8 %val
}
define i16 @test4(i16* %ptr) {
; PPC64LE-LABEL: test4:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lhz 3, 0(3)
; PPC64LE-NEXT: blr
%val = load atomic i16, i16* %ptr unordered, align 2
ret i16 %val
}
define i16 @test5(i16* %ptr) {
; PPC64LE-LABEL: test5:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lhz 3, 0(3)
; PPC64LE-NEXT: blr
%val = load atomic i16, i16* %ptr monotonic, align 2
ret i16 %val
}
define i16 @test6(i16* %ptr) {
; PPC64LE-LABEL: test6:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lhz 3, 0(3)
; PPC64LE-NEXT: cmpd 7, 3, 3
; PPC64LE-NEXT: bne- 7, .+4
; PPC64LE-NEXT: isync
; PPC64LE-NEXT: blr
%val = load atomic i16, i16* %ptr acquire, align 2
ret i16 %val
}
define i16 @test7(i16* %ptr) {
; PPC64LE-LABEL: test7:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: lhz 3, 0(3)
; PPC64LE-NEXT: cmpd 7, 3, 3
; PPC64LE-NEXT: bne- 7, .+4
; PPC64LE-NEXT: isync
; PPC64LE-NEXT: blr
%val = load atomic i16, i16* %ptr seq_cst, align 2
ret i16 %val
}
define i32 @test8(i32* %ptr) {
; PPC64LE-LABEL: test8:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwz 3, 0(3)
; PPC64LE-NEXT: blr
%val = load atomic i32, i32* %ptr unordered, align 4
ret i32 %val
}
define i32 @test9(i32* %ptr) {
; PPC64LE-LABEL: test9:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwz 3, 0(3)
; PPC64LE-NEXT: blr
%val = load atomic i32, i32* %ptr monotonic, align 4
ret i32 %val
}
define i32 @test10(i32* %ptr) {
; PPC64LE-LABEL: test10:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwz 3, 0(3)
; PPC64LE-NEXT: cmpd 7, 3, 3
; PPC64LE-NEXT: bne- 7, .+4
; PPC64LE-NEXT: isync
; PPC64LE-NEXT: blr
%val = load atomic i32, i32* %ptr acquire, align 4
ret i32 %val
}
define i32 @test11(i32* %ptr) {
; PPC64LE-LABEL: test11:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: lwz 3, 0(3)
; PPC64LE-NEXT: cmpd 7, 3, 3
; PPC64LE-NEXT: bne- 7, .+4
; PPC64LE-NEXT: isync
; PPC64LE-NEXT: blr
%val = load atomic i32, i32* %ptr seq_cst, align 4
ret i32 %val
}
define i64 @test12(i64* %ptr) {
; PPC64LE-LABEL: test12:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: ld 3, 0(3)
; PPC64LE-NEXT: blr
%val = load atomic i64, i64* %ptr unordered, align 8
ret i64 %val
}
define i64 @test13(i64* %ptr) {
; PPC64LE-LABEL: test13:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: ld 3, 0(3)
; PPC64LE-NEXT: blr
%val = load atomic i64, i64* %ptr monotonic, align 8
ret i64 %val
}
define i64 @test14(i64* %ptr) {
; PPC64LE-LABEL: test14:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: ld 3, 0(3)
; PPC64LE-NEXT: cmpd 7, 3, 3
; PPC64LE-NEXT: bne- 7, .+4
; PPC64LE-NEXT: isync
; PPC64LE-NEXT: blr
%val = load atomic i64, i64* %ptr acquire, align 8
ret i64 %val
}
define i64 @test15(i64* %ptr) {
; PPC64LE-LABEL: test15:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: ld 3, 0(3)
; PPC64LE-NEXT: cmpd 7, 3, 3
; PPC64LE-NEXT: bne- 7, .+4
; PPC64LE-NEXT: isync
; PPC64LE-NEXT: blr
%val = load atomic i64, i64* %ptr seq_cst, align 8
ret i64 %val
}
define void @test16(i8* %ptr, i8 %val) {
; PPC64LE-LABEL: test16:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: stb 4, 0(3)
; PPC64LE-NEXT: blr
store atomic i8 %val, i8* %ptr unordered, align 1
ret void
}
define void @test17(i8* %ptr, i8 %val) {
; PPC64LE-LABEL: test17:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: stb 4, 0(3)
; PPC64LE-NEXT: blr
store atomic i8 %val, i8* %ptr monotonic, align 1
ret void
}
define void @test18(i8* %ptr, i8 %val) {
; PPC64LE-LABEL: test18:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: stb 4, 0(3)
; PPC64LE-NEXT: blr
store atomic i8 %val, i8* %ptr release, align 1
ret void
}
define void @test19(i8* %ptr, i8 %val) {
; PPC64LE-LABEL: test19:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: stb 4, 0(3)
; PPC64LE-NEXT: blr
store atomic i8 %val, i8* %ptr seq_cst, align 1
ret void
}
define void @test20(i16* %ptr, i16 %val) {
; PPC64LE-LABEL: test20:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sth 4, 0(3)
; PPC64LE-NEXT: blr
store atomic i16 %val, i16* %ptr unordered, align 2
ret void
}
define void @test21(i16* %ptr, i16 %val) {
; PPC64LE-LABEL: test21:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sth 4, 0(3)
; PPC64LE-NEXT: blr
store atomic i16 %val, i16* %ptr monotonic, align 2
ret void
}
define void @test22(i16* %ptr, i16 %val) {
; PPC64LE-LABEL: test22:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: sth 4, 0(3)
; PPC64LE-NEXT: blr
store atomic i16 %val, i16* %ptr release, align 2
ret void
}
define void @test23(i16* %ptr, i16 %val) {
; PPC64LE-LABEL: test23:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: sth 4, 0(3)
; PPC64LE-NEXT: blr
store atomic i16 %val, i16* %ptr seq_cst, align 2
ret void
}
define void @test24(i32* %ptr, i32 %val) {
; PPC64LE-LABEL: test24:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: stw 4, 0(3)
; PPC64LE-NEXT: blr
store atomic i32 %val, i32* %ptr unordered, align 4
ret void
}
define void @test25(i32* %ptr, i32 %val) {
; PPC64LE-LABEL: test25:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: stw 4, 0(3)
; PPC64LE-NEXT: blr
store atomic i32 %val, i32* %ptr monotonic, align 4
ret void
}
define void @test26(i32* %ptr, i32 %val) {
; PPC64LE-LABEL: test26:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: stw 4, 0(3)
; PPC64LE-NEXT: blr
store atomic i32 %val, i32* %ptr release, align 4
ret void
}
define void @test27(i32* %ptr, i32 %val) {
; PPC64LE-LABEL: test27:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: stw 4, 0(3)
; PPC64LE-NEXT: blr
store atomic i32 %val, i32* %ptr seq_cst, align 4
ret void
}
define void @test28(i64* %ptr, i64 %val) {
; PPC64LE-LABEL: test28:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: std 4, 0(3)
; PPC64LE-NEXT: blr
store atomic i64 %val, i64* %ptr unordered, align 8
ret void
}
define void @test29(i64* %ptr, i64 %val) {
; PPC64LE-LABEL: test29:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: std 4, 0(3)
; PPC64LE-NEXT: blr
store atomic i64 %val, i64* %ptr monotonic, align 8
ret void
}
define void @test30(i64* %ptr, i64 %val) {
; PPC64LE-LABEL: test30:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: std 4, 0(3)
; PPC64LE-NEXT: blr
store atomic i64 %val, i64* %ptr release, align 8
ret void
}
define void @test31(i64* %ptr, i64 %val) {
; PPC64LE-LABEL: test31:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: std 4, 0(3)
; PPC64LE-NEXT: blr
store atomic i64 %val, i64* %ptr seq_cst, align 8
ret void
}
define void @test32() {
; PPC64LE-LABEL: test32:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
fence acquire
ret void
}
define void @test33() {
; PPC64LE-LABEL: test33:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
fence release
ret void
}
define void @test34() {
; PPC64LE-LABEL: test34:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
fence acq_rel
ret void
}
define void @test35() {
; PPC64LE-LABEL: test35:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: blr
fence seq_cst
ret void
}
define void @test36() {
; PPC64LE-LABEL: test36:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
fence syncscope("singlethread") acquire
ret void
}
define void @test37() {
; PPC64LE-LABEL: test37:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
fence syncscope("singlethread") release
ret void
}
define void @test38() {
; PPC64LE-LABEL: test38:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
fence syncscope("singlethread") acq_rel
ret void
}
define void @test39() {
; PPC64LE-LABEL: test39:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: blr
fence syncscope("singlethread") seq_cst
ret void
}
define void @test40(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test40:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
; PPC64LE-NEXT: b .LBB40_2
; PPC64LE-NEXT: .p2align 5
; PPC64LE-NEXT: .LBB40_1:
; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: beqlr 0
; PPC64LE-NEXT: .LBB40_2:
; PPC64LE-NEXT: lbarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: beq 0, .LBB40_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: blr
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val monotonic monotonic
ret void
}
define void @test41(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test41:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
; PPC64LE-NEXT: .LBB41_1:
; PPC64LE-NEXT: lbarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB41_4
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB41_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB41_4:
; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acquire monotonic
ret void
}
define void @test42(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test42:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
; PPC64LE-NEXT: .LBB42_1:
; PPC64LE-NEXT: lbarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB42_4
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB42_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB42_4:
; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acquire acquire
ret void
}
define void @test43(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test43:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: b .LBB43_2
; PPC64LE-NEXT: .p2align 5
; PPC64LE-NEXT: .LBB43_1:
; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: beqlr 0
; PPC64LE-NEXT: .LBB43_2:
; PPC64LE-NEXT: lbarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: beq 0, .LBB43_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: blr
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val release monotonic
ret void
}
define void @test44(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test44:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: b .LBB44_2
; PPC64LE-NEXT: .p2align 5
; PPC64LE-NEXT: .LBB44_1:
; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: beqlr 0
; PPC64LE-NEXT: .LBB44_2:
; PPC64LE-NEXT: lbarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: beq 0, .LBB44_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: blr
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val release acquire
ret void
}
define void @test45(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test45:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB45_1:
; PPC64LE-NEXT: lbarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB45_4
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB45_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB45_4:
; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acq_rel monotonic
ret void
}
define void @test46(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test46:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB46_1:
; PPC64LE-NEXT: lbarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB46_4
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB46_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB46_4:
; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acq_rel acquire
ret void
}
define void @test47(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test47:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB47_1:
; PPC64LE-NEXT: lbarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB47_4
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB47_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB47_4:
; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val seq_cst monotonic
ret void
}
define void @test48(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test48:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB48_1:
; PPC64LE-NEXT: lbarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB48_4
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB48_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB48_4:
; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val seq_cst acquire
ret void
}
define void @test49(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test49:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB49_1:
; PPC64LE-NEXT: lbarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB49_4
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB49_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB49_4:
; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val seq_cst seq_cst
ret void
}
define void @test50(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test50:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
; PPC64LE-NEXT: b .LBB50_2
; PPC64LE-NEXT: .p2align 5
; PPC64LE-NEXT: .LBB50_1:
; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: beqlr 0
; PPC64LE-NEXT: .LBB50_2:
; PPC64LE-NEXT: lharx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: beq 0, .LBB50_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: blr
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val monotonic monotonic
ret void
}
define void @test51(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test51:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
; PPC64LE-NEXT: .LBB51_1:
; PPC64LE-NEXT: lharx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB51_4
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB51_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB51_4:
; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acquire monotonic
ret void
}
define void @test52(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test52:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
; PPC64LE-NEXT: .LBB52_1:
; PPC64LE-NEXT: lharx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB52_4
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB52_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB52_4:
; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acquire acquire
ret void
}
define void @test53(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test53:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: b .LBB53_2
; PPC64LE-NEXT: .p2align 5
; PPC64LE-NEXT: .LBB53_1:
; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: beqlr 0
; PPC64LE-NEXT: .LBB53_2:
; PPC64LE-NEXT: lharx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: beq 0, .LBB53_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: blr
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val release monotonic
ret void
}
define void @test54(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test54:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: b .LBB54_2
; PPC64LE-NEXT: .p2align 5
; PPC64LE-NEXT: .LBB54_1:
; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: beqlr 0
; PPC64LE-NEXT: .LBB54_2:
; PPC64LE-NEXT: lharx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: beq 0, .LBB54_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: blr
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val release acquire
ret void
}
define void @test55(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test55:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB55_1:
; PPC64LE-NEXT: lharx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB55_4
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB55_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB55_4:
; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acq_rel monotonic
ret void
}
define void @test56(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test56:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB56_1:
; PPC64LE-NEXT: lharx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB56_4
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB56_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB56_4:
; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acq_rel acquire
ret void
}
define void @test57(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test57:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB57_1:
; PPC64LE-NEXT: lharx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB57_4
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB57_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB57_4:
; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val seq_cst monotonic
ret void
}
define void @test58(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test58:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB58_1:
; PPC64LE-NEXT: lharx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB58_4
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB58_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB58_4:
; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val seq_cst acquire
ret void
}
define void @test59(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test59:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB59_1:
; PPC64LE-NEXT: lharx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB59_4
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB59_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB59_4:
; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val seq_cst seq_cst
ret void
}
define void @test60(i32* %ptr, i32 %cmp, i32 %val) {
; PPC64LE-LABEL: test60:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: b .LBB60_2
; PPC64LE-NEXT: .p2align 5
; PPC64LE-NEXT: .LBB60_1:
; PPC64LE-NEXT: stwcx. 5, 0, 3
; PPC64LE-NEXT: beqlr 0
; PPC64LE-NEXT: .LBB60_2:
; PPC64LE-NEXT: lwarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: beq 0, .LBB60_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: stwcx. 6, 0, 3
; PPC64LE-NEXT: blr
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val monotonic monotonic
ret void
}
define void @test61(i32* %ptr, i32 %cmp, i32 %val) {
; PPC64LE-LABEL: test61:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: .LBB61_1:
; PPC64LE-NEXT: lwarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB61_4
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stwcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB61_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB61_4:
; PPC64LE-NEXT: stwcx. 6, 0, 3
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val acquire monotonic
ret void
}
define void @test62(i32* %ptr, i32 %cmp, i32 %val) {
; PPC64LE-LABEL: test62:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: .LBB62_1:
; PPC64LE-NEXT: lwarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB62_4
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stwcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB62_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB62_4:
; PPC64LE-NEXT: stwcx. 6, 0, 3
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val acquire acquire
ret void
}
define void @test63(i32* %ptr, i32 %cmp, i32 %val) {
; PPC64LE-LABEL: test63:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: b .LBB63_2
; PPC64LE-NEXT: .p2align 5
; PPC64LE-NEXT: .LBB63_1:
; PPC64LE-NEXT: stwcx. 5, 0, 3
; PPC64LE-NEXT: beqlr 0
; PPC64LE-NEXT: .LBB63_2:
; PPC64LE-NEXT: lwarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: beq 0, .LBB63_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: stwcx. 6, 0, 3
; PPC64LE-NEXT: blr
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val release monotonic
ret void
}
define void @test64(i32* %ptr, i32 %cmp, i32 %val) {
; PPC64LE-LABEL: test64:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: b .LBB64_2
; PPC64LE-NEXT: .p2align 5
; PPC64LE-NEXT: .LBB64_1:
; PPC64LE-NEXT: stwcx. 5, 0, 3
; PPC64LE-NEXT: beqlr 0
; PPC64LE-NEXT: .LBB64_2:
; PPC64LE-NEXT: lwarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: beq 0, .LBB64_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: stwcx. 6, 0, 3
; PPC64LE-NEXT: blr
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val release acquire
ret void
}
define void @test65(i32* %ptr, i32 %cmp, i32 %val) {
; PPC64LE-LABEL: test65:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB65_1:
; PPC64LE-NEXT: lwarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB65_4
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stwcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB65_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB65_4:
; PPC64LE-NEXT: stwcx. 6, 0, 3
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val acq_rel monotonic
ret void
}
define void @test66(i32* %ptr, i32 %cmp, i32 %val) {
; PPC64LE-LABEL: test66:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB66_1:
; PPC64LE-NEXT: lwarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB66_4
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stwcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB66_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB66_4:
; PPC64LE-NEXT: stwcx. 6, 0, 3
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val acq_rel acquire
ret void
}
define void @test67(i32* %ptr, i32 %cmp, i32 %val) {
; PPC64LE-LABEL: test67:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB67_1:
; PPC64LE-NEXT: lwarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB67_4
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stwcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB67_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB67_4:
; PPC64LE-NEXT: stwcx. 6, 0, 3
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val seq_cst monotonic
ret void
}
define void @test68(i32* %ptr, i32 %cmp, i32 %val) {
; PPC64LE-LABEL: test68:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB68_1:
; PPC64LE-NEXT: lwarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB68_4
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stwcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB68_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB68_4:
; PPC64LE-NEXT: stwcx. 6, 0, 3
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val seq_cst acquire
ret void
}
define void @test69(i32* %ptr, i32 %cmp, i32 %val) {
; PPC64LE-LABEL: test69:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB69_1:
; PPC64LE-NEXT: lwarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB69_4
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stwcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB69_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB69_4:
; PPC64LE-NEXT: stwcx. 6, 0, 3
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val seq_cst seq_cst
ret void
}
define void @test70(i64* %ptr, i64 %cmp, i64 %val) {
; PPC64LE-LABEL: test70:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: b .LBB70_2
; PPC64LE-NEXT: .p2align 5
; PPC64LE-NEXT: .LBB70_1:
; PPC64LE-NEXT: stdcx. 5, 0, 3
; PPC64LE-NEXT: beqlr 0
; PPC64LE-NEXT: .LBB70_2:
; PPC64LE-NEXT: ldarx 6, 0, 3
; PPC64LE-NEXT: cmpd 4, 6
; PPC64LE-NEXT: beq 0, .LBB70_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: stdcx. 6, 0, 3
; PPC64LE-NEXT: blr
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val monotonic monotonic
ret void
}
define void @test71(i64* %ptr, i64 %cmp, i64 %val) {
; PPC64LE-LABEL: test71:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: .LBB71_1:
; PPC64LE-NEXT: ldarx 6, 0, 3
; PPC64LE-NEXT: cmpd 4, 6
; PPC64LE-NEXT: bne 0, .LBB71_4
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stdcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB71_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB71_4:
; PPC64LE-NEXT: stdcx. 6, 0, 3
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val acquire monotonic
ret void
}
define void @test72(i64* %ptr, i64 %cmp, i64 %val) {
; PPC64LE-LABEL: test72:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: .LBB72_1:
; PPC64LE-NEXT: ldarx 6, 0, 3
; PPC64LE-NEXT: cmpd 4, 6
; PPC64LE-NEXT: bne 0, .LBB72_4
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stdcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB72_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB72_4:
; PPC64LE-NEXT: stdcx. 6, 0, 3
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val acquire acquire
ret void
}
define void @test73(i64* %ptr, i64 %cmp, i64 %val) {
; PPC64LE-LABEL: test73:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: b .LBB73_2
; PPC64LE-NEXT: .p2align 5
; PPC64LE-NEXT: .LBB73_1:
; PPC64LE-NEXT: stdcx. 5, 0, 3
; PPC64LE-NEXT: beqlr 0
; PPC64LE-NEXT: .LBB73_2:
; PPC64LE-NEXT: ldarx 6, 0, 3
; PPC64LE-NEXT: cmpd 4, 6
; PPC64LE-NEXT: beq 0, .LBB73_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: stdcx. 6, 0, 3
; PPC64LE-NEXT: blr
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val release monotonic
ret void
}
define void @test74(i64* %ptr, i64 %cmp, i64 %val) {
; PPC64LE-LABEL: test74:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: b .LBB74_2
; PPC64LE-NEXT: .p2align 5
; PPC64LE-NEXT: .LBB74_1:
; PPC64LE-NEXT: stdcx. 5, 0, 3
; PPC64LE-NEXT: beqlr 0
; PPC64LE-NEXT: .LBB74_2:
; PPC64LE-NEXT: ldarx 6, 0, 3
; PPC64LE-NEXT: cmpd 4, 6
; PPC64LE-NEXT: beq 0, .LBB74_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: stdcx. 6, 0, 3
; PPC64LE-NEXT: blr
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val release acquire
ret void
}
define void @test75(i64* %ptr, i64 %cmp, i64 %val) {
; PPC64LE-LABEL: test75:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB75_1:
; PPC64LE-NEXT: ldarx 6, 0, 3
; PPC64LE-NEXT: cmpd 4, 6
; PPC64LE-NEXT: bne 0, .LBB75_4
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stdcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB75_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB75_4:
; PPC64LE-NEXT: stdcx. 6, 0, 3
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val acq_rel monotonic
ret void
}
define void @test76(i64* %ptr, i64 %cmp, i64 %val) {
; PPC64LE-LABEL: test76:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB76_1:
; PPC64LE-NEXT: ldarx 6, 0, 3
; PPC64LE-NEXT: cmpd 4, 6
; PPC64LE-NEXT: bne 0, .LBB76_4
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stdcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB76_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB76_4:
; PPC64LE-NEXT: stdcx. 6, 0, 3
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val acq_rel acquire
ret void
}
define void @test77(i64* %ptr, i64 %cmp, i64 %val) {
; PPC64LE-LABEL: test77:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB77_1:
; PPC64LE-NEXT: ldarx 6, 0, 3
; PPC64LE-NEXT: cmpd 4, 6
; PPC64LE-NEXT: bne 0, .LBB77_4
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stdcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB77_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB77_4:
; PPC64LE-NEXT: stdcx. 6, 0, 3
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val seq_cst monotonic
ret void
}
define void @test78(i64* %ptr, i64 %cmp, i64 %val) {
; PPC64LE-LABEL: test78:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB78_1:
; PPC64LE-NEXT: ldarx 6, 0, 3
; PPC64LE-NEXT: cmpd 4, 6
; PPC64LE-NEXT: bne 0, .LBB78_4
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stdcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB78_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB78_4:
; PPC64LE-NEXT: stdcx. 6, 0, 3
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val seq_cst acquire
ret void
}
define void @test79(i64* %ptr, i64 %cmp, i64 %val) {
; PPC64LE-LABEL: test79:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB79_1:
; PPC64LE-NEXT: ldarx 6, 0, 3
; PPC64LE-NEXT: cmpd 4, 6
; PPC64LE-NEXT: bne 0, .LBB79_4
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stdcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB79_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB79_4:
; PPC64LE-NEXT: stdcx. 6, 0, 3
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val seq_cst seq_cst
ret void
}
define void @test80(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test80:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
; PPC64LE-NEXT: b .LBB80_2
; PPC64LE-NEXT: .p2align 5
; PPC64LE-NEXT: .LBB80_1:
; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: beqlr 0
; PPC64LE-NEXT: .LBB80_2:
; PPC64LE-NEXT: lbarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: beq 0, .LBB80_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: blr
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") monotonic monotonic
ret void
}
define void @test81(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test81:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
; PPC64LE-NEXT: .LBB81_1:
; PPC64LE-NEXT: lbarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB81_4
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB81_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB81_4:
; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") acquire monotonic
ret void
}
define void @test82(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test82:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
; PPC64LE-NEXT: .LBB82_1:
; PPC64LE-NEXT: lbarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB82_4
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB82_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB82_4:
; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") acquire acquire
ret void
}
define void @test83(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test83:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: b .LBB83_2
; PPC64LE-NEXT: .p2align 5
; PPC64LE-NEXT: .LBB83_1:
; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: beqlr 0
; PPC64LE-NEXT: .LBB83_2:
; PPC64LE-NEXT: lbarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: beq 0, .LBB83_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: blr
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") release monotonic
ret void
}
define void @test84(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test84:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: b .LBB84_2
; PPC64LE-NEXT: .p2align 5
; PPC64LE-NEXT: .LBB84_1:
; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: beqlr 0
; PPC64LE-NEXT: .LBB84_2:
; PPC64LE-NEXT: lbarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: beq 0, .LBB84_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: blr
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") release acquire
ret void
}
define void @test85(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test85:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB85_1:
; PPC64LE-NEXT: lbarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB85_4
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB85_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB85_4:
; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") acq_rel monotonic
ret void
}
define void @test86(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test86:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB86_1:
; PPC64LE-NEXT: lbarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB86_4
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB86_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB86_4:
; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") acq_rel acquire
ret void
}
define void @test87(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test87:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB87_1:
; PPC64LE-NEXT: lbarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB87_4
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB87_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB87_4:
; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") seq_cst monotonic
ret void
}
define void @test88(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test88:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB88_1:
; PPC64LE-NEXT: lbarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB88_4
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB88_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB88_4:
; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") seq_cst acquire
ret void
}
define void @test89(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test89:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB89_1:
; PPC64LE-NEXT: lbarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB89_4
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB89_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB89_4:
; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") seq_cst seq_cst
ret void
}
define void @test90(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test90:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
; PPC64LE-NEXT: b .LBB90_2
; PPC64LE-NEXT: .p2align 5
; PPC64LE-NEXT: .LBB90_1:
; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: beqlr 0
; PPC64LE-NEXT: .LBB90_2:
; PPC64LE-NEXT: lharx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: beq 0, .LBB90_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: blr
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") monotonic monotonic
ret void
}
define void @test91(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test91:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
; PPC64LE-NEXT: .LBB91_1:
; PPC64LE-NEXT: lharx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB91_4
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB91_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB91_4:
; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") acquire monotonic
ret void
}
define void @test92(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test92:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
; PPC64LE-NEXT: .LBB92_1:
; PPC64LE-NEXT: lharx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB92_4
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB92_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB92_4:
; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") acquire acquire
ret void
}
define void @test93(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test93:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: b .LBB93_2
; PPC64LE-NEXT: .p2align 5
; PPC64LE-NEXT: .LBB93_1:
; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: beqlr 0
; PPC64LE-NEXT: .LBB93_2:
; PPC64LE-NEXT: lharx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: beq 0, .LBB93_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: blr
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") release monotonic
ret void
}
define void @test94(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test94:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: b .LBB94_2
; PPC64LE-NEXT: .p2align 5
; PPC64LE-NEXT: .LBB94_1:
; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: beqlr 0
; PPC64LE-NEXT: .LBB94_2:
; PPC64LE-NEXT: lharx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: beq 0, .LBB94_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: blr
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") release acquire
ret void
}
define void @test95(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test95:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB95_1:
; PPC64LE-NEXT: lharx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB95_4
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB95_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB95_4:
; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") acq_rel monotonic
ret void
}
define void @test96(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test96:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB96_1:
; PPC64LE-NEXT: lharx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB96_4
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB96_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB96_4:
; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") acq_rel acquire
ret void
}
define void @test97(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test97:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB97_1:
; PPC64LE-NEXT: lharx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB97_4
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB97_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB97_4:
; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") seq_cst monotonic
ret void
}
define void @test98(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test98:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB98_1:
; PPC64LE-NEXT: lharx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB98_4
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB98_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB98_4:
; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") seq_cst acquire
ret void
}
define void @test99(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test99:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB99_1:
; PPC64LE-NEXT: lharx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB99_4
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB99_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB99_4:
; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") seq_cst seq_cst
ret void
}
define void @test100(i32* %ptr, i32 %cmp, i32 %val) {
; PPC64LE-LABEL: test100:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: b .LBB100_2
; PPC64LE-NEXT: .p2align 5
; PPC64LE-NEXT: .LBB100_1:
; PPC64LE-NEXT: stwcx. 5, 0, 3
; PPC64LE-NEXT: beqlr 0
; PPC64LE-NEXT: .LBB100_2:
; PPC64LE-NEXT: lwarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: beq 0, .LBB100_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: stwcx. 6, 0, 3
; PPC64LE-NEXT: blr
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val syncscope("singlethread") monotonic monotonic
ret void
}
define void @test101(i32* %ptr, i32 %cmp, i32 %val) {
; PPC64LE-LABEL: test101:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: .LBB101_1:
; PPC64LE-NEXT: lwarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB101_4
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stwcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB101_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB101_4:
; PPC64LE-NEXT: stwcx. 6, 0, 3
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val syncscope("singlethread") acquire monotonic
ret void
}
define void @test102(i32* %ptr, i32 %cmp, i32 %val) {
; PPC64LE-LABEL: test102:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: .LBB102_1:
; PPC64LE-NEXT: lwarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB102_4
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stwcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB102_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB102_4:
; PPC64LE-NEXT: stwcx. 6, 0, 3
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val syncscope("singlethread") acquire acquire
ret void
}
define void @test103(i32* %ptr, i32 %cmp, i32 %val) {
; PPC64LE-LABEL: test103:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: b .LBB103_2
; PPC64LE-NEXT: .p2align 5
; PPC64LE-NEXT: .LBB103_1:
; PPC64LE-NEXT: stwcx. 5, 0, 3
; PPC64LE-NEXT: beqlr 0
; PPC64LE-NEXT: .LBB103_2:
; PPC64LE-NEXT: lwarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: beq 0, .LBB103_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: stwcx. 6, 0, 3
; PPC64LE-NEXT: blr
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val syncscope("singlethread") release monotonic
ret void
}
define void @test104(i32* %ptr, i32 %cmp, i32 %val) {
; PPC64LE-LABEL: test104:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: b .LBB104_2
; PPC64LE-NEXT: .p2align 5
; PPC64LE-NEXT: .LBB104_1:
; PPC64LE-NEXT: stwcx. 5, 0, 3
; PPC64LE-NEXT: beqlr 0
; PPC64LE-NEXT: .LBB104_2:
; PPC64LE-NEXT: lwarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: beq 0, .LBB104_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: stwcx. 6, 0, 3
; PPC64LE-NEXT: blr
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val syncscope("singlethread") release acquire
ret void
}
define void @test105(i32* %ptr, i32 %cmp, i32 %val) {
; PPC64LE-LABEL: test105:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB105_1:
; PPC64LE-NEXT: lwarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB105_4
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stwcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB105_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB105_4:
; PPC64LE-NEXT: stwcx. 6, 0, 3
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val syncscope("singlethread") acq_rel monotonic
ret void
}
define void @test106(i32* %ptr, i32 %cmp, i32 %val) {
; PPC64LE-LABEL: test106:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB106_1:
; PPC64LE-NEXT: lwarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB106_4
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stwcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB106_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB106_4:
; PPC64LE-NEXT: stwcx. 6, 0, 3
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val syncscope("singlethread") acq_rel acquire
ret void
}
define void @test107(i32* %ptr, i32 %cmp, i32 %val) {
; PPC64LE-LABEL: test107:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB107_1:
; PPC64LE-NEXT: lwarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB107_4
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stwcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB107_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB107_4:
; PPC64LE-NEXT: stwcx. 6, 0, 3
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val syncscope("singlethread") seq_cst monotonic
ret void
}
define void @test108(i32* %ptr, i32 %cmp, i32 %val) {
; PPC64LE-LABEL: test108:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB108_1:
; PPC64LE-NEXT: lwarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB108_4
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stwcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB108_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB108_4:
; PPC64LE-NEXT: stwcx. 6, 0, 3
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val syncscope("singlethread") seq_cst acquire
ret void
}
define void @test109(i32* %ptr, i32 %cmp, i32 %val) {
; PPC64LE-LABEL: test109:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB109_1:
; PPC64LE-NEXT: lwarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB109_4
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stwcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB109_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB109_4:
; PPC64LE-NEXT: stwcx. 6, 0, 3
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val syncscope("singlethread") seq_cst seq_cst
ret void
}
define void @test110(i64* %ptr, i64 %cmp, i64 %val) {
; PPC64LE-LABEL: test110:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: b .LBB110_2
; PPC64LE-NEXT: .p2align 5
; PPC64LE-NEXT: .LBB110_1:
; PPC64LE-NEXT: stdcx. 5, 0, 3
; PPC64LE-NEXT: beqlr 0
; PPC64LE-NEXT: .LBB110_2:
; PPC64LE-NEXT: ldarx 6, 0, 3
; PPC64LE-NEXT: cmpd 4, 6
; PPC64LE-NEXT: beq 0, .LBB110_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: stdcx. 6, 0, 3
; PPC64LE-NEXT: blr
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val syncscope("singlethread") monotonic monotonic
ret void
}
define void @test111(i64* %ptr, i64 %cmp, i64 %val) {
; PPC64LE-LABEL: test111:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: .LBB111_1:
; PPC64LE-NEXT: ldarx 6, 0, 3
; PPC64LE-NEXT: cmpd 4, 6
; PPC64LE-NEXT: bne 0, .LBB111_4
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stdcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB111_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB111_4:
; PPC64LE-NEXT: stdcx. 6, 0, 3
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val syncscope("singlethread") acquire monotonic
ret void
}
define void @test112(i64* %ptr, i64 %cmp, i64 %val) {
; PPC64LE-LABEL: test112:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: .LBB112_1:
; PPC64LE-NEXT: ldarx 6, 0, 3
; PPC64LE-NEXT: cmpd 4, 6
; PPC64LE-NEXT: bne 0, .LBB112_4
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stdcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB112_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB112_4:
; PPC64LE-NEXT: stdcx. 6, 0, 3
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val syncscope("singlethread") acquire acquire
ret void
}
define void @test113(i64* %ptr, i64 %cmp, i64 %val) {
; PPC64LE-LABEL: test113:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: b .LBB113_2
; PPC64LE-NEXT: .p2align 5
; PPC64LE-NEXT: .LBB113_1:
; PPC64LE-NEXT: stdcx. 5, 0, 3
; PPC64LE-NEXT: beqlr 0
; PPC64LE-NEXT: .LBB113_2:
; PPC64LE-NEXT: ldarx 6, 0, 3
; PPC64LE-NEXT: cmpd 4, 6
; PPC64LE-NEXT: beq 0, .LBB113_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: stdcx. 6, 0, 3
; PPC64LE-NEXT: blr
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val syncscope("singlethread") release monotonic
ret void
}
define void @test114(i64* %ptr, i64 %cmp, i64 %val) {
; PPC64LE-LABEL: test114:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: b .LBB114_2
; PPC64LE-NEXT: .p2align 5
; PPC64LE-NEXT: .LBB114_1:
; PPC64LE-NEXT: stdcx. 5, 0, 3
; PPC64LE-NEXT: beqlr 0
; PPC64LE-NEXT: .LBB114_2:
; PPC64LE-NEXT: ldarx 6, 0, 3
; PPC64LE-NEXT: cmpd 4, 6
; PPC64LE-NEXT: beq 0, .LBB114_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: stdcx. 6, 0, 3
; PPC64LE-NEXT: blr
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val syncscope("singlethread") release acquire
ret void
}
define void @test115(i64* %ptr, i64 %cmp, i64 %val) {
; PPC64LE-LABEL: test115:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB115_1:
; PPC64LE-NEXT: ldarx 6, 0, 3
; PPC64LE-NEXT: cmpd 4, 6
; PPC64LE-NEXT: bne 0, .LBB115_4
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stdcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB115_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB115_4:
; PPC64LE-NEXT: stdcx. 6, 0, 3
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val syncscope("singlethread") acq_rel monotonic
ret void
}
define void @test116(i64* %ptr, i64 %cmp, i64 %val) {
; PPC64LE-LABEL: test116:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB116_1:
; PPC64LE-NEXT: ldarx 6, 0, 3
; PPC64LE-NEXT: cmpd 4, 6
; PPC64LE-NEXT: bne 0, .LBB116_4
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stdcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB116_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB116_4:
; PPC64LE-NEXT: stdcx. 6, 0, 3
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val syncscope("singlethread") acq_rel acquire
ret void
}
define void @test117(i64* %ptr, i64 %cmp, i64 %val) {
; PPC64LE-LABEL: test117:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB117_1:
; PPC64LE-NEXT: ldarx 6, 0, 3
; PPC64LE-NEXT: cmpd 4, 6
; PPC64LE-NEXT: bne 0, .LBB117_4
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stdcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB117_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB117_4:
; PPC64LE-NEXT: stdcx. 6, 0, 3
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val syncscope("singlethread") seq_cst monotonic
ret void
}
define void @test118(i64* %ptr, i64 %cmp, i64 %val) {
; PPC64LE-LABEL: test118:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB118_1:
; PPC64LE-NEXT: ldarx 6, 0, 3
; PPC64LE-NEXT: cmpd 4, 6
; PPC64LE-NEXT: bne 0, .LBB118_4
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stdcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB118_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB118_4:
; PPC64LE-NEXT: stdcx. 6, 0, 3
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val syncscope("singlethread") seq_cst acquire
ret void
}
define void @test119(i64* %ptr, i64 %cmp, i64 %val) {
; PPC64LE-LABEL: test119:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB119_1:
; PPC64LE-NEXT: ldarx 6, 0, 3
; PPC64LE-NEXT: cmpd 4, 6
; PPC64LE-NEXT: bne 0, .LBB119_4
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stdcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB119_1
; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB119_4:
; PPC64LE-NEXT: stdcx. 6, 0, 3
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val syncscope("singlethread") seq_cst seq_cst
ret void
}
define i8 @test120(i8* %ptr, i8 %val) {
; PPC64LE-LABEL: test120:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: .LBB120_1:
; PPC64LE-NEXT: lbarx 5, 0, 3
; PPC64LE-NEXT: stbcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB120_1
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr
%ret = atomicrmw xchg i8* %ptr, i8 %val monotonic
ret i8 %ret
}
define i8 @test121(i8* %ptr, i8 %val) {
; PPC64LE-LABEL: test121:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: mr 5, 3
; PPC64LE-NEXT: .LBB121_1:
; PPC64LE-NEXT: lbarx 3, 0, 5
; PPC64LE-NEXT: stbcx. 4, 0, 5
; PPC64LE-NEXT: bne 0, .LBB121_1
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%ret = atomicrmw xchg i8* %ptr, i8 %val acquire
ret i8 %ret
}
define i8 @test122(i8* %ptr, i8 %val) {
; PPC64LE-LABEL: test122:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB122_1:
; PPC64LE-NEXT: lbarx 5, 0, 3
; PPC64LE-NEXT: stbcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB122_1
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr
%ret = atomicrmw xchg i8* %ptr, i8 %val release
ret i8 %ret
}
define i8 @test123(i8* %ptr, i8 %val) {
; PPC64LE-LABEL: test123:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB123_1:
; PPC64LE-NEXT: lbarx 5, 0, 3
; PPC64LE-NEXT: stbcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB123_1
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%ret = atomicrmw xchg i8* %ptr, i8 %val acq_rel
ret i8 %ret
}
define i8 @test124(i8* %ptr, i8 %val) {
; PPC64LE-LABEL: test124:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB124_1:
; PPC64LE-NEXT: lbarx 5, 0, 3
; PPC64LE-NEXT: stbcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB124_1
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%ret = atomicrmw xchg i8* %ptr, i8 %val seq_cst
ret i8 %ret
}
define i16 @test125(i16* %ptr, i16 %val) {
; PPC64LE-LABEL: test125:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: .LBB125_1:
; PPC64LE-NEXT: lharx 5, 0, 3
; PPC64LE-NEXT: sthcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB125_1
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr
%ret = atomicrmw xchg i16* %ptr, i16 %val monotonic
ret i16 %ret
}
define i16 @test126(i16* %ptr, i16 %val) {
; PPC64LE-LABEL: test126:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: mr 5, 3
; PPC64LE-NEXT: .LBB126_1:
; PPC64LE-NEXT: lharx 3, 0, 5
; PPC64LE-NEXT: sthcx. 4, 0, 5
; PPC64LE-NEXT: bne 0, .LBB126_1
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%ret = atomicrmw xchg i16* %ptr, i16 %val acquire
ret i16 %ret
}
define i16 @test127(i16* %ptr, i16 %val) {
; PPC64LE-LABEL: test127:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB127_1:
; PPC64LE-NEXT: lharx 5, 0, 3
; PPC64LE-NEXT: sthcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB127_1
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr
%ret = atomicrmw xchg i16* %ptr, i16 %val release
ret i16 %ret
}
define i16 @test128(i16* %ptr, i16 %val) {
; PPC64LE-LABEL: test128:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB128_1:
; PPC64LE-NEXT: lharx 5, 0, 3
; PPC64LE-NEXT: sthcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB128_1
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%ret = atomicrmw xchg i16* %ptr, i16 %val acq_rel
ret i16 %ret
}
define i16 @test129(i16* %ptr, i16 %val) {
; PPC64LE-LABEL: test129:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB129_1:
; PPC64LE-NEXT: lharx 5, 0, 3
; PPC64LE-NEXT: sthcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB129_1
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%ret = atomicrmw xchg i16* %ptr, i16 %val seq_cst
ret i16 %ret
}
define i32 @test130(i32* %ptr, i32 %val) {
; PPC64LE-LABEL: test130:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: .LBB130_1:
; PPC64LE-NEXT: lwarx 5, 0, 3
; PPC64LE-NEXT: stwcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB130_1
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr
%ret = atomicrmw xchg i32* %ptr, i32 %val monotonic
ret i32 %ret
}
define i32 @test131(i32* %ptr, i32 %val) {
; PPC64LE-LABEL: test131:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: mr 5, 3
; PPC64LE-NEXT: .LBB131_1:
; PPC64LE-NEXT: lwarx 3, 0, 5
; PPC64LE-NEXT: stwcx. 4, 0, 5
; PPC64LE-NEXT: bne 0, .LBB131_1
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%ret = atomicrmw xchg i32* %ptr, i32 %val acquire
ret i32 %ret
}
define i32 @test132(i32* %ptr, i32 %val) {
; PPC64LE-LABEL: test132:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB132_1:
; PPC64LE-NEXT: lwarx 5, 0, 3
; PPC64LE-NEXT: stwcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB132_1
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr
%ret = atomicrmw xchg i32* %ptr, i32 %val release
ret i32 %ret
}
define i32 @test133(i32* %ptr, i32 %val) {
; PPC64LE-LABEL: test133:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB133_1:
; PPC64LE-NEXT: lwarx 5, 0, 3
; PPC64LE-NEXT: stwcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB133_1
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%ret = atomicrmw xchg i32* %ptr, i32 %val acq_rel
ret i32 %ret
}
define i32 @test134(i32* %ptr, i32 %val) {
; PPC64LE-LABEL: test134:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB134_1:
; PPC64LE-NEXT: lwarx 5, 0, 3
; PPC64LE-NEXT: stwcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB134_1
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%ret = atomicrmw xchg i32* %ptr, i32 %val seq_cst
ret i32 %ret
}
define i64 @test135(i64* %ptr, i64 %val) {
; PPC64LE-LABEL: test135:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: .LBB135_1:
; PPC64LE-NEXT: ldarx 5, 0, 3
; PPC64LE-NEXT: stdcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB135_1
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr
%ret = atomicrmw xchg i64* %ptr, i64 %val monotonic
ret i64 %ret
}
define i64 @test136(i64* %ptr, i64 %val) {
; PPC64LE-LABEL: test136:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: mr 5, 3
; PPC64LE-NEXT: .LBB136_1:
; PPC64LE-NEXT: ldarx 3, 0, 5
; PPC64LE-NEXT: stdcx. 4, 0, 5
; PPC64LE-NEXT: bne 0, .LBB136_1
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%ret = atomicrmw xchg i64* %ptr, i64 %val acquire
ret i64 %ret
}
define i64 @test137(i64* %ptr, i64 %val) {
; PPC64LE-LABEL: test137:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB137_1:
; PPC64LE-NEXT: ldarx 5, 0, 3
; PPC64LE-NEXT: stdcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB137_1
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr
%ret = atomicrmw xchg i64* %ptr, i64 %val release
ret i64 %ret
}
define i64 @test138(i64* %ptr, i64 %val) {
; PPC64LE-LABEL: test138:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB138_1:
; PPC64LE-NEXT: ldarx 5, 0, 3
; PPC64LE-NEXT: stdcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB138_1
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%ret = atomicrmw xchg i64* %ptr, i64 %val acq_rel
ret i64 %ret
}
define i64 @test139(i64* %ptr, i64 %val) {
; PPC64LE-LABEL: test139:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB139_1:
; PPC64LE-NEXT: ldarx 5, 0, 3
; PPC64LE-NEXT: stdcx. 4, 0, 3
; PPC64LE-NEXT: bne 0, .LBB139_1
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%ret = atomicrmw xchg i64* %ptr, i64 %val seq_cst
ret i64 %ret
}
define i8 @test140(i8* %ptr, i8 %val) {
; PPC64LE-LABEL: test140:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: .LBB140_1:
; PPC64LE-NEXT: lbarx 5, 0, 3
; PPC64LE-NEXT: add 6, 4, 5
; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB140_1
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr
%ret = atomicrmw add i8* %ptr, i8 %val monotonic
ret i8 %ret
}
define i8 @test141(i8* %ptr, i8 %val) {
; PPC64LE-LABEL: test141:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: mr 5, 3
; PPC64LE-NEXT: .LBB141_1:
; PPC64LE-NEXT: lbarx 3, 0, 5
; PPC64LE-NEXT: add 6, 4, 3
; PPC64LE-NEXT: stbcx. 6, 0, 5
; PPC64LE-NEXT: bne 0, .LBB141_1
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%ret = atomicrmw add i8* %ptr, i8 %val acquire
ret i8 %ret
}
define i8 @test142(i8* %ptr, i8 %val) {
; PPC64LE-LABEL: test142:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB142_1:
; PPC64LE-NEXT: lbarx 5, 0, 3
; PPC64LE-NEXT: add 6, 4, 5
; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB142_1
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr
%ret = atomicrmw add i8* %ptr, i8 %val release
ret i8 %ret
}
define i8 @test143(i8* %ptr, i8 %val) {
; PPC64LE-LABEL: test143:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB143_1:
; PPC64LE-NEXT: lbarx 5, 0, 3
; PPC64LE-NEXT: add 6, 4, 5
; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB143_1
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%ret = atomicrmw add i8* %ptr, i8 %val acq_rel
ret i8 %ret
}
define i8 @test144(i8* %ptr, i8 %val) {
; PPC64LE-LABEL: test144:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB144_1:
; PPC64LE-NEXT: lbarx 5, 0, 3
; PPC64LE-NEXT: add 6, 4, 5
; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB144_1
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%ret = atomicrmw add i8* %ptr, i8 %val seq_cst
ret i8 %ret
}
define i16 @test145(i16* %ptr, i16 %val) {
; PPC64LE-LABEL: test145:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: .LBB145_1:
; PPC64LE-NEXT: lharx 5, 0, 3
; PPC64LE-NEXT: add 6, 4, 5
; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB145_1
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr
%ret = atomicrmw add i16* %ptr, i16 %val monotonic
ret i16 %ret
}
define i16 @test146(i16* %ptr, i16 %val) {
; PPC64LE-LABEL: test146:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: mr 5, 3
; PPC64LE-NEXT: .LBB146_1:
; PPC64LE-NEXT: lharx 3, 0, 5
; PPC64LE-NEXT: add 6, 4, 3
; PPC64LE-NEXT: sthcx. 6, 0, 5
; PPC64LE-NEXT: bne 0, .LBB146_1
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%ret = atomicrmw add i16* %ptr, i16 %val acquire
ret i16 %ret
}
define i16 @test147(i16* %ptr, i16 %val) {
; PPC64LE-LABEL: test147:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB147_1:
; PPC64LE-NEXT: lharx 5, 0, 3
; PPC64LE-NEXT: add 6, 4, 5
; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB147_1
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr
%ret = atomicrmw add i16* %ptr, i16 %val release
ret i16 %ret
}
define i16 @test148(i16* %ptr, i16 %val) {
; PPC64LE-LABEL: test148:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB148_1:
; PPC64LE-NEXT: lharx 5, 0, 3
; PPC64LE-NEXT: add 6, 4, 5
; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB148_1
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%ret = atomicrmw add i16* %ptr, i16 %val acq_rel
ret i16 %ret
}
define i16 @test149(i16* %ptr, i16 %val) {
; PPC64LE-LABEL: test149:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB149_1:
; PPC64LE-NEXT: lharx 5, 0, 3
; PPC64LE-NEXT: add 6, 4, 5
; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB149_1
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%ret = atomicrmw add i16* %ptr, i16 %val seq_cst
ret i16 %ret
}
define i32 @test150(i32* %ptr, i32 %val) {
; PPC64LE-LABEL: test150:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: .LBB150_1:
; PPC64LE-NEXT: lwarx 5, 0, 3
; PPC64LE-NEXT: add 6, 4, 5
; PPC64LE-NEXT: stwcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB150_1
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr
%ret = atomicrmw add i32* %ptr, i32 %val monotonic
ret i32 %ret
}
define i32 @test151(i32* %ptr, i32 %val) {
; PPC64LE-LABEL: test151:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: mr 5, 3
; PPC64LE-NEXT: .LBB151_1:
; PPC64LE-NEXT: lwarx 3, 0, 5
; PPC64LE-NEXT: add 6, 4, 3
; PPC64LE-NEXT: stwcx. 6, 0, 5
; PPC64LE-NEXT: bne 0, .LBB151_1
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%ret = atomicrmw add i32* %ptr, i32 %val acquire
ret i32 %ret
}
define i32 @test152(i32* %ptr, i32 %val) {
; PPC64LE-LABEL: test152:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB152_1:
; PPC64LE-NEXT: lwarx 5, 0, 3
; PPC64LE-NEXT: add 6, 4, 5
; PPC64LE-NEXT: stwcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB152_1
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr
%ret = atomicrmw add i32* %ptr, i32 %val release
ret i32 %ret
}
define i32 @test153(i32* %ptr, i32 %val) {
; PPC64LE-LABEL: test153:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB153_1:
; PPC64LE-NEXT: lwarx 5, 0, 3
; PPC64LE-NEXT: add 6, 4, 5
; PPC64LE-NEXT: stwcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB153_1
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%ret = atomicrmw add i32* %ptr, i32 %val acq_rel
ret i32 %ret
}
define i32 @test154(i32* %ptr, i32 %val) {
; PPC64LE-LABEL: test154:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB154_1:
; PPC64LE-NEXT: lwarx 5, 0, 3
; PPC64LE-NEXT: add 6, 4, 5
; PPC64LE-NEXT: stwcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB154_1
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%ret = atomicrmw add i32* %ptr, i32 %val seq_cst
ret i32 %ret
}
define i64 @test155(i64* %ptr, i64 %val) {
; PPC64LE-LABEL: test155:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: .LBB155_1:
; PPC64LE-NEXT: ldarx 5, 0, 3
; PPC64LE-NEXT: add 6, 4, 5
; PPC64LE-NEXT: stdcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB155_1
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr
%ret = atomicrmw add i64* %ptr, i64 %val monotonic
ret i64 %ret
}
define i64 @test156(i64* %ptr, i64 %val) {
; PPC64LE-LABEL: test156:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: mr 5, 3
; PPC64LE-NEXT: .LBB156_1:
; PPC64LE-NEXT: ldarx 3, 0, 5
; PPC64LE-NEXT: add 6, 4, 3
; PPC64LE-NEXT: stdcx. 6, 0, 5
; PPC64LE-NEXT: bne 0, .LBB156_1
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%ret = atomicrmw add i64* %ptr, i64 %val acquire
ret i64 %ret
}
define i64 @test157(i64* %ptr, i64 %val) {
; PPC64LE-LABEL: test157:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB157_1:
; PPC64LE-NEXT: ldarx 5, 0, 3
; PPC64LE-NEXT: add 6, 4, 5
; PPC64LE-NEXT: stdcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB157_1
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr
%ret = atomicrmw add i64* %ptr, i64 %val release
ret i64 %ret
}
define i64 @test158(i64* %ptr, i64 %val) {
; PPC64LE-LABEL: test158:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB158_1:
; PPC64LE-NEXT: ldarx 5, 0, 3
; PPC64LE-NEXT: add 6, 4, 5
; PPC64LE-NEXT: stdcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB158_1
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%ret = atomicrmw add i64* %ptr, i64 %val acq_rel
ret i64 %ret
}
define i64 @test159(i64* %ptr, i64 %val) {
; PPC64LE-LABEL: test159:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB159_1:
; PPC64LE-NEXT: ldarx 5, 0, 3
; PPC64LE-NEXT: add 6, 4, 5
; PPC64LE-NEXT: stdcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB159_1
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%ret = atomicrmw add i64* %ptr, i64 %val seq_cst
ret i64 %ret
}
define i8 @test160(i8* %ptr, i8 %val) {
; PPC64LE-LABEL: test160:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: .LBB160_1:
; PPC64LE-NEXT: lbarx 5, 0, 3
; PPC64LE-NEXT: subf 6, 4, 5
; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB160_1
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr
%ret = atomicrmw sub i8* %ptr, i8 %val monotonic
ret i8 %ret
}
define i8 @test161(i8* %ptr, i8 %val) {
; PPC64LE-LABEL: test161:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: mr 5, 3
; PPC64LE-NEXT: .LBB161_1:
; PPC64LE-NEXT: lbarx 3, 0, 5
; PPC64LE-NEXT: subf 6, 4, 3
; PPC64LE-NEXT: stbcx. 6, 0, 5
; PPC64LE-NEXT: bne 0, .LBB161_1
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%ret = atomicrmw sub i8* %ptr, i8 %val acquire
ret i8 %ret
}
define i8 @test162(i8* %ptr, i8 %val) {
; PPC64LE-LABEL: test162:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB162_1:
; PPC64LE-NEXT: lbarx 5, 0, 3
; PPC64LE-NEXT: subf 6, 4, 5
; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB162_1
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr
%ret = atomicrmw sub i8* %ptr, i8 %val release
ret i8 %ret
}
define i8 @test163(i8* %ptr, i8 %val) {
; PPC64LE-LABEL: test163:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB163_1:
; PPC64LE-NEXT: lbarx 5, 0, 3
; PPC64LE-NEXT: subf 6, 4, 5
; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB163_1
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%ret = atomicrmw sub i8* %ptr, i8 %val acq_rel
ret i8 %ret
}
define i8 @test164(i8* %ptr, i8 %val) {
; PPC64LE-LABEL: test164:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB164_1:
; PPC64LE-NEXT: lbarx 5, 0, 3
; PPC64LE-NEXT: subf 6, 4, 5
; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB164_1
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%ret = atomicrmw sub i8* %ptr, i8 %val seq_cst
ret i8 %ret
}
define i16 @test165(i16* %ptr, i16 %val) {
; PPC64LE-LABEL: test165:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: .LBB165_1:
; PPC64LE-NEXT: lharx 5, 0, 3
; PPC64LE-NEXT: subf 6, 4, 5
; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB165_1
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr
%ret = atomicrmw sub i16* %ptr, i16 %val monotonic
ret i16 %ret
}
define i16 @test166(i16* %ptr, i16 %val) {
; PPC64LE-LABEL: test166:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: mr 5, 3
; PPC64LE-NEXT: .LBB166_1:
; PPC64LE-NEXT: lharx 3, 0, 5
; PPC64LE-NEXT: subf 6, 4, 3
; PPC64LE-NEXT: sthcx. 6, 0, 5
; PPC64LE-NEXT: bne 0, .LBB166_1
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%ret = atomicrmw sub i16* %ptr, i16 %val acquire
ret i16 %ret
}
define i16 @test167(i16* %ptr, i16 %val) {
; PPC64LE-LABEL: test167:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB167_1:
; PPC64LE-NEXT: lharx 5, 0, 3
; PPC64LE-NEXT: subf 6, 4, 5
; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB167_1
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr
%ret = atomicrmw sub i16* %ptr, i16 %val release
ret i16 %ret
}
define i16 @test168(i16* %ptr, i16 %val) {
; PPC64LE-LABEL: test168:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB168_1:
; PPC64LE-NEXT: lharx 5, 0, 3
; PPC64LE-NEXT: subf 6, 4, 5
; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB168_1
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%ret = atomicrmw sub i16* %ptr, i16 %val acq_rel
ret i16 %ret
}
define i16 @test169(i16* %ptr, i16 %val) {
; PPC64LE-LABEL: test169:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB169_1:
; PPC64LE-NEXT: lharx 5, 0, 3
; PPC64LE-NEXT: subf 6, 4, 5
; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB169_1
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%ret = atomicrmw sub i16* %ptr, i16 %val seq_cst
ret i16 %ret
}
define i32 @test170(i32* %ptr, i32 %val) {
; PPC64LE-LABEL: test170:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: .LBB170_1:
; PPC64LE-NEXT: lwarx 5, 0, 3
; PPC64LE-NEXT: subf 6, 4, 5
; PPC64LE-NEXT: stwcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB170_1
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr
%ret = atomicrmw sub i32* %ptr, i32 %val monotonic
ret i32 %ret
}
define i32 @test171(i32* %ptr, i32 %val) {
; PPC64LE-LABEL: test171:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: mr 5, 3
; PPC64LE-NEXT: .LBB171_1:
; PPC64LE-NEXT: lwarx 3, 0, 5
; PPC64LE-NEXT: subf 6, 4, 3
; PPC64LE-NEXT: stwcx. 6, 0, 5
; PPC64LE-NEXT: bne 0, .LBB171_1
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%ret = atomicrmw sub i32* %ptr, i32 %val acquire
ret i32 %ret
}
define i32 @test172(i32* %ptr, i32 %val) {
; PPC64LE-LABEL: test172:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB172_1:
; PPC64LE-NEXT: lwarx 5, 0, 3
; PPC64LE-NEXT: subf 6, 4, 5
; PPC64LE-NEXT: stwcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB172_1
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr
%ret = atomicrmw sub i32* %ptr, i32 %val release
ret i32 %ret
}
define i32 @test173(i32* %ptr, i32 %val) {
; PPC64LE-LABEL: test173:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB173_1:
; PPC64LE-NEXT: lwarx 5, 0, 3
; PPC64LE-NEXT: subf 6, 4, 5
; PPC64LE-NEXT: stwcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB173_1
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%ret = atomicrmw sub i32* %ptr, i32 %val acq_rel
ret i32 %ret
}
define i32 @test174(i32* %ptr, i32 %val) {
; PPC64LE-LABEL: test174:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB174_1:
; PPC64LE-NEXT: lwarx 5, 0, 3
; PPC64LE-NEXT: subf 6, 4, 5
; PPC64LE-NEXT: stwcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB174_1
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%ret = atomicrmw sub i32* %ptr, i32 %val seq_cst
ret i32 %ret
}
define i64 @test175(i64* %ptr, i64 %val) {
; PPC64LE-LABEL: test175:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: .LBB175_1:
; PPC64LE-NEXT: ldarx 5, 0, 3
; PPC64LE-NEXT: sub 6, 5, 4
; PPC64LE-NEXT: stdcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB175_1
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr
%ret = atomicrmw sub i64* %ptr, i64 %val monotonic
ret i64 %ret
}
define i64 @test176(i64* %ptr, i64 %val) {
; PPC64LE-LABEL: test176:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: mr 5, 3
; PPC64LE-NEXT: .LBB176_1:
; PPC64LE-NEXT: ldarx 3, 0, 5
; PPC64LE-NEXT: sub 6, 3, 4
; PPC64LE-NEXT: stdcx. 6, 0, 5
; PPC64LE-NEXT: bne 0, .LBB176_1
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%ret = atomicrmw sub i64* %ptr, i64 %val acquire
ret i64 %ret
}
define i64 @test177(i64* %ptr, i64 %val) {
; PPC64LE-LABEL: test177:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB177_1:
; PPC64LE-NEXT: ldarx 5, 0, 3
; PPC64LE-NEXT: sub 6, 5, 4
; PPC64LE-NEXT: stdcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB177_1
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr
%ret = atomicrmw sub i64* %ptr, i64 %val release
ret i64 %ret
}
define i64 @test178(i64* %ptr, i64 %val) {
; PPC64LE-LABEL: test178:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB178_1:
; PPC64LE-NEXT: ldarx 5, 0, 3
; PPC64LE-NEXT: sub 6, 5, 4
; PPC64LE-NEXT: stdcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB178_1
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%ret = atomicrmw sub i64* %ptr, i64 %val acq_rel
ret i64 %ret
}
define i64 @test179(i64* %ptr, i64 %val) {
; PPC64LE-LABEL: test179:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB179_1:
; PPC64LE-NEXT: ldarx 5, 0, 3
; PPC64LE-NEXT: sub 6, 5, 4
; PPC64LE-NEXT: stdcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB179_1
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%ret = atomicrmw sub i64* %ptr, i64 %val seq_cst
ret i64 %ret
}
define i8 @test180(i8* %ptr, i8 %val) {
; PPC64LE-LABEL: test180:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: .LBB180_1:
; PPC64LE-NEXT: lbarx 5, 0, 3
; PPC64LE-NEXT: and 6, 4, 5
; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB180_1
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr
%ret = atomicrmw and i8* %ptr, i8 %val monotonic
ret i8 %ret
}
define i8 @test181(i8* %ptr, i8 %val) {
; PPC64LE-LABEL: test181:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: mr 5, 3
; PPC64LE-NEXT: .LBB181_1:
; PPC64LE-NEXT: lbarx 3, 0, 5
; PPC64LE-NEXT: and 6, 4, 3
; PPC64LE-NEXT: stbcx. 6, 0, 5
; PPC64LE-NEXT: bne 0, .LBB181_1
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%ret = atomicrmw and i8* %ptr, i8 %val acquire
ret i8 %ret
}
define i8 @test182(i8* %ptr, i8 %val) {
; PPC64LE-LABEL: test182:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB182_1:
; PPC64LE-NEXT: lbarx 5, 0, 3
; PPC64LE-NEXT: and 6, 4, 5
; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB182_1
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr
%ret = atomicrmw and i8* %ptr, i8 %val release
ret i8 %ret
}
define i8 @test183(i8* %ptr, i8 %val) {
; PPC64LE-LABEL: test183:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB183_1:
; PPC64LE-NEXT: lbarx 5, 0, 3
; PPC64LE-NEXT: and 6, 4, 5
; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB183_1
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%ret = atomicrmw and i8* %ptr, i8 %val acq_rel
ret i8 %ret
}
define i8 @test184(i8* %ptr, i8 %val) {
; PPC64LE-LABEL: test184:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB184_1:
; PPC64LE-NEXT: lbarx 5, 0, 3
; PPC64LE-NEXT: and 6, 4, 5
; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB184_1
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr
%ret = atomicrmw and i8* %ptr, i8 %val seq_cst
ret i8 %ret
}
define i16 @test185(i16* %ptr, i16 %val) {
; PPC64LE-LABEL: test185:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: .LBB185_1:
; PPC64LE-NEXT: lharx 5, 0, 3
; PPC64LE-NEXT: and 6, 4, 5
; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: bne 0, .LBB185_1
; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: mr 3, 5
; PPC64LE-NEXT: blr
%ret = atomicrmw and i16* %ptr, i16 %val monotonic
ret i16 %ret
}
define i16 @test186(i16* %ptr, i16 %val) {
; PPC64LE-LABEL: test186:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: mr 5, 3
; PPC64LE-NEXT: .LBB186_1: