test/CodeGen/AMDGPU/GlobalISel/inst-select-select.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN

---
name:            select_s64_scc
legalized:       true
regBankSelected: true

body: |
  bb.0:
    liveins:  $sgpr0, $sgpr1, $sgpr2_sgpr3, $sgpr4_sgpr5

    ; GCN-LABEL: name: select_s64_scc
    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
    ; GCN: [[COPY2:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
    ; GCN: [[COPY3:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5
    ; GCN: S_CMP_EQ_U32 [[COPY]], [[COPY1]], implicit-def $scc
    ; GCN: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $scc
    ; GCN: $scc = COPY [[COPY4]]
    ; GCN: [[S_CSELECT_B64_:%[0-9]+]]:sreg_64 = S_CSELECT_B64 [[COPY2]], [[COPY3]], implicit $scc
    ; GCN: S_ENDPGM 0, implicit [[S_CSELECT_B64_]]
    %0:sgpr(s32) = COPY $sgpr0
    %1:sgpr(s32) = COPY $sgpr1
    %2:sgpr(s64) = COPY $sgpr2_sgpr3
    %3:sgpr(s64) = COPY $sgpr4_sgpr5
    %4:scc(s1) = G_ICMP intpred(eq), %0, %1
    %5:sgpr(s64) = G_SELECT %4, %2, %3
    S_ENDPGM 0, implicit %5

...

---
name:            select_v4s16_scc
legalized:       true
regBankSelected: true

body: |
  bb.0:
    liveins:  $sgpr0, $sgpr1, $sgpr2_sgpr3, $sgpr4_sgpr5

    ; GCN-LABEL: name: select_v4s16_scc
    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
    ; GCN: [[COPY2:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
    ; GCN: [[COPY3:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5
    ; GCN: S_CMP_EQ_U32 [[COPY]], [[COPY1]], implicit-def $scc
    ; GCN: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $scc
    ; GCN: $scc = COPY [[COPY4]]
    ; GCN: [[S_CSELECT_B64_:%[0-9]+]]:sreg_64 = S_CSELECT_B64 [[COPY2]], [[COPY3]], implicit $scc
    ; GCN: S_ENDPGM 0, implicit [[S_CSELECT_B64_]]
    %0:sgpr(s32) = COPY $sgpr0
    %1:sgpr(s32) = COPY $sgpr1
    %2:sgpr(<4 x s16>) = COPY $sgpr2_sgpr3
    %3:sgpr(<4 x s16>) = COPY $sgpr4_sgpr5
    %4:scc(s1) = G_ICMP intpred(eq), %0, %1
    %5:sgpr(<4 x s16>) = G_SELECT %4, %2, %3
    S_ENDPGM 0, implicit %5

...

---
name:            select_s16_scc
legalized:       true
regBankSelected: true

body: |
  bb.0:
    liveins:  $sgpr0, $sgpr1, $sgpr2, $sgpr3

    ; GCN-LABEL: name: select_s16_scc
    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
    ; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
    ; GCN: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
    ; GCN: S_CMP_EQ_U32 [[COPY2]], [[COPY3]], implicit-def $scc
    ; GCN: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $scc
    ; GCN: $scc = COPY [[COPY4]]
    ; GCN: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[COPY]], [[COPY1]], implicit $scc
    ; GCN: S_ENDPGM 0, implicit [[S_CSELECT_B32_]]
    %0:sgpr(s32) = COPY $sgpr0
    %1:sgpr(s32) = COPY $sgpr1
    %2:sgpr(s32) = COPY $sgpr2
    %3:sgpr(s32) = COPY $sgpr3
    %4:sgpr(s16) = G_TRUNC %0
    %5:sgpr(s16) = G_TRUNC %1
    %6:scc(s1) = G_ICMP intpred(eq), %2, %3
    %7:sgpr(s16) = G_SELECT %6, %4, %5
    S_ENDPGM 0, implicit %7

...

---
name:            select_v2s16_scc
legalized:       true
regBankSelected: true

body: |
  bb.0:
    liveins:  $sgpr0, $sgpr1, $sgpr2, $sgpr3

    ; GCN-LABEL: name: select_v2s16_scc
    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
    ; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
    ; GCN: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
    ; GCN: S_CMP_EQ_U32 [[COPY]], [[COPY1]], implicit-def $scc
    ; GCN: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $scc
    ; GCN: $scc = COPY [[COPY4]]
    ; GCN: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[COPY2]], [[COPY3]], implicit $scc
    ; GCN: S_ENDPGM 0, implicit [[S_CSELECT_B32_]]
    %0:sgpr(s32) = COPY $sgpr0
    %1:sgpr(s32) = COPY $sgpr1
    %2:sgpr(<2 x s16>) = COPY $sgpr2
    %3:sgpr(<2 x s16>) = COPY $sgpr3
    %4:scc(s1) = G_ICMP intpred(eq), %0, %1
    %5:sgpr(<2 x s16>) = G_SELECT %4, %2, %3
    S_ENDPGM 0, implicit %5

...

---
name:            select_s16_vcc
legalized:       true
regBankSelected: true

body: |
  bb.0:
    liveins:  $vgpr0, $vgpr1, $vgpr2, $vgpr3

    ; GCN-LABEL: name: select_s16_vcc
    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
    ; GCN: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
    ; GCN: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[COPY2]], [[COPY3]], implicit $exec
    ; GCN: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY1]], 0, [[COPY]], [[V_CMP_EQ_U32_e64_]], implicit $exec
    ; GCN: S_ENDPGM 0, implicit [[V_CNDMASK_B32_e64_]]
    %0:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr1
    %2:vgpr(s32) = COPY $vgpr2
    %3:vgpr(s32) = COPY $vgpr3
    %4:vgpr(s16) = G_TRUNC %0
    %5:vgpr(s16) = G_TRUNC %1
    %6:vcc(s1) = G_ICMP intpred(eq), %2, %3
    %7:vgpr(s16) = G_SELECT %6, %4, %5
    S_ENDPGM 0, implicit %7

...

---
name:            select_v2s16_vcc
legalized:       true
regBankSelected: true

body: |
  bb.0:
    liveins:  $vgpr0, $vgpr1, $vgpr2, $vgpr3

    ; GCN-LABEL: name: select_v2s16_vcc
    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
    ; GCN: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
    ; GCN: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[COPY1]], implicit $exec
    ; GCN: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY3]], 0, [[COPY2]], [[V_CMP_EQ_U32_e64_]], implicit $exec
    ; GCN: S_ENDPGM 0, implicit [[V_CNDMASK_B32_e64_]]
    %0:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr1
    %2:vgpr(<2 x s16>) = COPY $vgpr2
    %3:vgpr(<2 x s16>) = COPY $vgpr3
    %4:vcc(s1) = G_ICMP intpred(eq), %0, %1
    %5:vgpr(<2 x s16>) = G_SELECT %4, %2, %3
    S_ENDPGM 0, implicit %5

...