# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s  | FileCheck -check-prefix=WAVE64 %s
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s  | FileCheck -check-prefix=WAVE64 %s
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr="+wavefrontsize32" -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s  | FileCheck -check-prefix=WAVE32 %s

---

name:            or_s1_vcc_vcc_vcc
legalized:       true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins: $vgpr0, $vgpr1
    ; WAVE64-LABEL: name: or_s1_vcc_vcc_vcc
    ; WAVE64: liveins: $vgpr0, $vgpr1
    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; WAVE64: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
    ; WAVE64: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
    ; WAVE64: [[V_CMP_EQ_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec
    ; WAVE64: [[S_OR_B64_:%[0-9]+]]:sreg_64 = S_OR_B64 [[V_CMP_EQ_U32_e64_]], [[V_CMP_EQ_U32_e64_1]]
    ; WAVE64: S_ENDPGM 0, implicit [[S_OR_B64_]]
    ; WAVE32-LABEL: name: or_s1_vcc_vcc_vcc
    ; WAVE32: liveins: $vgpr0, $vgpr1
    ; WAVE32: $vcc_hi = IMPLICIT_DEF
    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; WAVE32: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
    ; WAVE32: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_EQ_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
    ; WAVE32: [[V_CMP_EQ_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_EQ_U32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec
    ; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[V_CMP_EQ_U32_e64_]], [[V_CMP_EQ_U32_e64_1]]
    ; WAVE32: S_ENDPGM 0, implicit [[S_OR_B32_]]
    %0:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr1
    %2:vgpr(s32) = G_CONSTANT i32 0
    %3:vcc(s1) = G_ICMP intpred(eq), %0, %2
    %4:vcc(s1) = G_ICMP intpred(eq), %1, %2
    %5:vcc(s1) = G_OR %3, %4
    S_ENDPGM 0, implicit %5
...

---

name:            or_s1_sgpr_sgpr_sgpr
legalized:       true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins: $sgpr0, $sgpr1
    ; WAVE64-LABEL: name: or_s1_sgpr_sgpr_sgpr
    ; WAVE64: liveins: $sgpr0, $sgpr1
    ; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
    ; WAVE64: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[COPY1]]
    ; WAVE64: S_ENDPGM 0, implicit [[S_OR_B32_]]
    ; WAVE32-LABEL: name: or_s1_sgpr_sgpr_sgpr
    ; WAVE32: liveins: $sgpr0, $sgpr1
    ; WAVE32: $vcc_hi = IMPLICIT_DEF
    ; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
    ; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[COPY1]]
    ; WAVE32: S_ENDPGM 0, implicit [[S_OR_B32_]]
    %0:sgpr(s32) = COPY $sgpr0
    %1:sgpr(s32) = COPY $sgpr1
    %2:sgpr(s1) = G_TRUNC %0
    %3:sgpr(s1) = G_TRUNC %1
    %4:sgpr(s1) = G_OR %2, %3
    S_ENDPGM 0, implicit %4
...

---

name:            or_s1_scc_sgpr_sgpr
legalized:       true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins: $sgpr0, $sgpr1
    ; WAVE64-LABEL: name: or_s1_scc_sgpr_sgpr
    ; WAVE64: liveins: $sgpr0, $sgpr1
    ; WAVE64: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
    ; WAVE64: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
    ; WAVE64: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
    ; WAVE64: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
    ; WAVE64: [[OR:%[0-9]+]]:scc(s1) = G_OR [[TRUNC]], [[TRUNC1]]
    ; WAVE64: S_ENDPGM 0, implicit [[OR]](s1)
    ; WAVE32-LABEL: name: or_s1_scc_sgpr_sgpr
    ; WAVE32: liveins: $sgpr0, $sgpr1
    ; WAVE32: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
    ; WAVE32: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
    ; WAVE32: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
    ; WAVE32: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
    ; WAVE32: [[OR:%[0-9]+]]:scc(s1) = G_OR [[TRUNC]], [[TRUNC1]]
    ; WAVE32: S_ENDPGM 0, implicit [[OR]](s1)
    %0:sgpr(s32) = COPY $sgpr0
    %1:sgpr(s32) = COPY $sgpr1
    %2:sgpr(s1) = G_TRUNC %0
    %3:sgpr(s1) = G_TRUNC %1
    %4:scc(s1) = G_OR %2, %3
    S_ENDPGM 0, implicit %4
...

---

name:            or_s16_sgpr_sgpr_sgpr
legalized:       true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins: $sgpr0, $sgpr1
    ; WAVE64-LABEL: name: or_s16_sgpr_sgpr_sgpr
    ; WAVE64: liveins: $sgpr0, $sgpr1
    ; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
    ; WAVE64: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[COPY1]]
    ; WAVE64: S_ENDPGM 0, implicit [[S_OR_B32_]]
    ; WAVE32-LABEL: name: or_s16_sgpr_sgpr_sgpr
    ; WAVE32: liveins: $sgpr0, $sgpr1
    ; WAVE32: $vcc_hi = IMPLICIT_DEF
    ; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
    ; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[COPY1]]
    ; WAVE32: S_ENDPGM 0, implicit [[S_OR_B32_]]
    %0:sgpr(s32) = COPY $sgpr0
    %1:sgpr(s32) = COPY $sgpr1
    %2:sgpr(s16) = G_TRUNC %0
    %3:sgpr(s16) = G_TRUNC %1
    %4:sgpr(s16) = G_OR %2, %3
    S_ENDPGM 0, implicit %4
...

---

name:            or_s16_vgpr_vgpr_vgpr
legalized:       true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins: $vgpr0, $vgpr1
    ; WAVE64-LABEL: name: or_s16_vgpr_vgpr_vgpr
    ; WAVE64: liveins: $vgpr0, $vgpr1
    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; WAVE64: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[COPY]], [[COPY1]], implicit $exec
    ; WAVE64: S_ENDPGM 0, implicit [[V_OR_B32_e64_]]
    ; WAVE32-LABEL: name: or_s16_vgpr_vgpr_vgpr
    ; WAVE32: liveins: $vgpr0, $vgpr1
    ; WAVE32: $vcc_hi = IMPLICIT_DEF
    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; WAVE32: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[COPY]], [[COPY1]], implicit $exec
    ; WAVE32: S_ENDPGM 0, implicit [[V_OR_B32_e64_]]
    %0:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr1
    %2:vgpr(s16) = G_TRUNC %0
    %3:vgpr(s16) = G_TRUNC %1
    %4:vgpr(s16) = G_OR %2, %3
    S_ENDPGM 0, implicit %4
...

---

name:            or_s32_sgpr_sgpr_sgpr
legalized:       true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins: $sgpr0, $sgpr1
    ; WAVE64-LABEL: name: or_s32_sgpr_sgpr_sgpr
    ; WAVE64: liveins: $sgpr0, $sgpr1
    ; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
    ; WAVE64: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[COPY1]]
    ; WAVE64: S_ENDPGM 0, implicit [[S_OR_B32_]]
    ; WAVE32-LABEL: name: or_s32_sgpr_sgpr_sgpr
    ; WAVE32: liveins: $sgpr0, $sgpr1
    ; WAVE32: $vcc_hi = IMPLICIT_DEF
    ; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
    ; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[COPY1]]
    ; WAVE32: S_ENDPGM 0, implicit [[S_OR_B32_]]
    %0:sgpr(s32) = COPY $sgpr0
    %1:sgpr(s32) = COPY $sgpr1
    %2:sgpr(s32) = G_OR %0, %1
    S_ENDPGM 0, implicit %2
...

---

name:            or_s64_sgpr_sgpr_sgpr
legalized:       true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
    ; WAVE64-LABEL: name: or_s64_sgpr_sgpr_sgpr
    ; WAVE64: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
    ; WAVE64: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
    ; WAVE64: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
    ; WAVE64: [[S_OR_B64_:%[0-9]+]]:sreg_64 = S_OR_B64 [[COPY]], [[COPY1]]
    ; WAVE64: S_ENDPGM 0, implicit [[S_OR_B64_]]
    ; WAVE32-LABEL: name: or_s64_sgpr_sgpr_sgpr
    ; WAVE32: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
    ; WAVE32: $vcc_hi = IMPLICIT_DEF
    ; WAVE32: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
    ; WAVE32: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
    ; WAVE32: [[S_OR_B64_:%[0-9]+]]:sreg_64 = S_OR_B64 [[COPY]], [[COPY1]]
    ; WAVE32: S_ENDPGM 0, implicit [[S_OR_B64_]]
    %0:sgpr(s64) = COPY $sgpr0_sgpr1
    %1:sgpr(s64) = COPY $sgpr2_sgpr3
    %2:sgpr(s64) = G_OR %0, %1
    S_ENDPGM 0, implicit %2
...

---

name:            or_v2s16_sgpr_sgpr_sgpr
legalized:       true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins: $sgpr0, $sgpr1
    ; WAVE64-LABEL: name: or_v2s16_sgpr_sgpr_sgpr
    ; WAVE64: liveins: $sgpr0, $sgpr1
    ; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
    ; WAVE64: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[COPY1]]
    ; WAVE64: S_ENDPGM 0, implicit [[S_OR_B32_]]
    ; WAVE32-LABEL: name: or_v2s16_sgpr_sgpr_sgpr
    ; WAVE32: liveins: $sgpr0, $sgpr1
    ; WAVE32: $vcc_hi = IMPLICIT_DEF
    ; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
    ; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[COPY1]]
    ; WAVE32: S_ENDPGM 0, implicit [[S_OR_B32_]]
    %0:sgpr(<2 x s16>) = COPY $sgpr0
    %1:sgpr(<2 x s16>) = COPY $sgpr1
    %2:sgpr(<2 x s16>) = G_OR %0, %1
    S_ENDPGM 0, implicit %2
...

---

name:            or_v2s32_sgpr_sgpr_sgpr
legalized:       true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
    ; WAVE64-LABEL: name: or_v2s32_sgpr_sgpr_sgpr
    ; WAVE64: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
    ; WAVE64: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
    ; WAVE64: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
    ; WAVE64: [[S_OR_B64_:%[0-9]+]]:sreg_64 = S_OR_B64 [[COPY]], [[COPY1]]
    ; WAVE64: S_ENDPGM 0, implicit [[S_OR_B64_]]
    ; WAVE32-LABEL: name: or_v2s32_sgpr_sgpr_sgpr
    ; WAVE32: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
    ; WAVE32: $vcc_hi = IMPLICIT_DEF
    ; WAVE32: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
    ; WAVE32: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
    ; WAVE32: [[S_OR_B64_:%[0-9]+]]:sreg_64 = S_OR_B64 [[COPY]], [[COPY1]]
    ; WAVE32: S_ENDPGM 0, implicit [[S_OR_B64_]]
    %0:sgpr(<2 x s32>) = COPY $sgpr0_sgpr1
    %1:sgpr(<2 x s32>) = COPY $sgpr2_sgpr3
    %2:sgpr(<2 x s32>) = G_OR %0, %1
    S_ENDPGM 0, implicit %2
...

---

name:            or_v4s16_sgpr_sgpr_sgpr
legalized:       true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
    ; WAVE64-LABEL: name: or_v4s16_sgpr_sgpr_sgpr
    ; WAVE64: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
    ; WAVE64: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
    ; WAVE64: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
    ; WAVE64: [[S_OR_B64_:%[0-9]+]]:sreg_64 = S_OR_B64 [[COPY]], [[COPY1]]
    ; WAVE64: S_ENDPGM 0, implicit [[S_OR_B64_]]
    ; WAVE32-LABEL: name: or_v4s16_sgpr_sgpr_sgpr
    ; WAVE32: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
    ; WAVE32: $vcc_hi = IMPLICIT_DEF
    ; WAVE32: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
    ; WAVE32: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
    ; WAVE32: [[S_OR_B64_:%[0-9]+]]:sreg_64 = S_OR_B64 [[COPY]], [[COPY1]]
    ; WAVE32: S_ENDPGM 0, implicit [[S_OR_B64_]]
    %0:sgpr(<4 x s16>) = COPY $sgpr0_sgpr1
    %1:sgpr(<4 x s16>) = COPY $sgpr2_sgpr3
    %2:sgpr(<4 x s16>) = G_OR %0, %1
    S_ENDPGM 0, implicit %2
...

---

name:            or_s32_vgpr_vgpr_vgpr
legalized:       true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins: $vgpr0, $vgpr1
    ; WAVE64-LABEL: name: or_s32_vgpr_vgpr_vgpr
    ; WAVE64: liveins: $vgpr0, $vgpr1
    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; WAVE64: [[V_OR_B32_e32_:%[0-9]+]]:vgpr_32 = V_OR_B32_e32 [[COPY]], [[COPY1]], implicit $exec
    ; WAVE64: S_ENDPGM 0, implicit [[V_OR_B32_e32_]]
    ; WAVE32-LABEL: name: or_s32_vgpr_vgpr_vgpr
    ; WAVE32: liveins: $vgpr0, $vgpr1
    ; WAVE32: $vcc_hi = IMPLICIT_DEF
    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; WAVE32: [[V_OR_B32_e32_:%[0-9]+]]:vgpr_32 = V_OR_B32_e32 [[COPY]], [[COPY1]], implicit $exec
    ; WAVE32: S_ENDPGM 0, implicit [[V_OR_B32_e32_]]
    %0:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr1
    %2:vgpr(s32) = G_OR %0, %1
    S_ENDPGM 0, implicit %2
...

---

name:            or_v2s16_vgpr_vgpr_vgpr
legalized:       true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins: $vgpr0, $vgpr1
    ; WAVE64-LABEL: name: or_v2s16_vgpr_vgpr_vgpr
    ; WAVE64: liveins: $vgpr0, $vgpr1
    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; WAVE64: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[COPY]], [[COPY1]], implicit $exec
    ; WAVE64: S_ENDPGM 0, implicit [[V_OR_B32_e64_]]
    ; WAVE32-LABEL: name: or_v2s16_vgpr_vgpr_vgpr
    ; WAVE32: liveins: $vgpr0, $vgpr1
    ; WAVE32: $vcc_hi = IMPLICIT_DEF
    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; WAVE32: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[COPY]], [[COPY1]], implicit $exec
    ; WAVE32: S_ENDPGM 0, implicit [[V_OR_B32_e64_]]
    %0:vgpr(<2 x s16>) = COPY $vgpr0
    %1:vgpr(<2 x s16>) = COPY $vgpr1
    %2:vgpr(<2 x s16>) = G_OR %0, %1
    S_ENDPGM 0, implicit %2
...


# This should fail to select
---

name:            or_s64_vgpr_vgpr_vgpr
legalized:       true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
    ; WAVE64-LABEL: name: or_s64_vgpr_vgpr_vgpr
    ; WAVE64: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
    ; WAVE64: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3
    ; WAVE64: [[OR:%[0-9]+]]:vgpr(s64) = G_OR [[COPY]], [[COPY1]]
    ; WAVE64: S_ENDPGM 0, implicit [[OR]](s64)
    ; WAVE32-LABEL: name: or_s64_vgpr_vgpr_vgpr
    ; WAVE32: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
    ; WAVE32: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3
    ; WAVE32: [[OR:%[0-9]+]]:vgpr(s64) = G_OR [[COPY]], [[COPY1]]
    ; WAVE32: S_ENDPGM 0, implicit [[OR]](s64)
    %0:vgpr(s64) = COPY $vgpr0_vgpr1
    %1:vgpr(s64) = COPY $vgpr2_vgpr3
    %2:vgpr(s64) = G_OR %0, %1
    S_ENDPGM 0, implicit %2
...

---

name:            or_s1_vcc_undef_vcc_undef_vcc
legalized:       true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    ; WAVE64-LABEL: name: or_s1_vcc_undef_vcc_undef_vcc
    ; WAVE64: [[S_OR_B64_:%[0-9]+]]:sreg_64 = S_OR_B64 undef %1:sreg_64, undef %2:sreg_64
    ; WAVE64: S_ENDPGM 0, implicit [[S_OR_B64_]]
    ; WAVE32-LABEL: name: or_s1_vcc_undef_vcc_undef_vcc
    ; WAVE32: $vcc_hi = IMPLICIT_DEF
    ; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 undef %1:sreg_32, undef %2:sreg_32
    ; WAVE32: S_ENDPGM 0, implicit [[S_OR_B32_]]
    %2:vcc(s1) = G_OR undef %0:vcc(s1), undef %1:vcc(s1)
    S_ENDPGM 0, implicit %2
...

---

name:            or_s1_sgpr_undef_sgpr_undef_sgpr
legalized:       true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    ; WAVE64-LABEL: name: or_s1_sgpr_undef_sgpr_undef_sgpr
    ; WAVE64: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 undef %1:sreg_32, undef %2:sreg_32
    ; WAVE64: S_ENDPGM 0, implicit [[S_OR_B32_]]
    ; WAVE32-LABEL: name: or_s1_sgpr_undef_sgpr_undef_sgpr
    ; WAVE32: $vcc_hi = IMPLICIT_DEF
    ; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 undef %1:sreg_32, undef %2:sreg_32
    ; WAVE32: S_ENDPGM 0, implicit [[S_OR_B32_]]
    %2:sgpr(s1) = G_OR undef %0:sgpr(s1), undef %1:sgpr(s1)
    S_ENDPGM 0, implicit %2
...

---

name:            or_s1_vgpr_undef_vgpr_undef_vgpr
legalized:       true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    ; WAVE64-LABEL: name: or_s1_vgpr_undef_vgpr_undef_vgpr
    ; WAVE64: [[OR:%[0-9]+]]:vgpr(s1) = G_OR undef %1:vgpr, undef %2:vgpr
    ; WAVE64: S_ENDPGM 0, implicit [[OR]](s1)
    ; WAVE32-LABEL: name: or_s1_vgpr_undef_vgpr_undef_vgpr
    ; WAVE32: [[OR:%[0-9]+]]:vgpr(s1) = G_OR undef %1:vgpr, undef %2:vgpr
    ; WAVE32: S_ENDPGM 0, implicit [[OR]](s1)
    %2:vgpr(s1) = G_OR undef %0:vgpr(s1), undef %1:vgpr(s1)
    S_ENDPGM 0, implicit %2
...

---

name:            or_s1_vcc_copy_to_vcc
legalized:       true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins: $vgpr0, $vgpr1
    ; WAVE64-LABEL: name: or_s1_vcc_copy_to_vcc
    ; WAVE64: liveins: $vgpr0, $vgpr1
    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
    ; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[COPY1]], implicit $exec
    ; WAVE64: [[S_OR_B64_:%[0-9]+]]:sreg_64 = S_OR_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]
    ; WAVE64: S_ENDPGM 0, implicit [[S_OR_B64_]]
    ; WAVE32-LABEL: name: or_s1_vcc_copy_to_vcc
    ; WAVE32: liveins: $vgpr0, $vgpr1
    ; WAVE32: $vcc_hi = IMPLICIT_DEF
    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
    ; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[COPY1]], implicit $exec
    ; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]
    ; WAVE32: S_ENDPGM 0, implicit [[S_OR_B32_]]
    %0:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr1
    %2:vgpr(s1) = G_TRUNC %0
    %3:vgpr(s1) = G_TRUNC %1
    %4:vcc(s1) = COPY %2
    %5:vcc(s1) = COPY %3
    %6:vcc(s1) = G_OR %4, %5
    S_ENDPGM 0, implicit %6
...

# The selector for the copy of the or result may constrain the result
# register of the or, losing that it is a VCCRegBank context.

# Works for wave32, should fail for wave64
---
name:            copy_select_constrain_vcc_result_reg_wave32
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0

    ; WAVE64-LABEL: name: copy_select_constrain_vcc_result_reg_wave32
    ; WAVE64: liveins: $vgpr0
    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE64: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1
    ; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]]
    ; WAVE64: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY1]], [[S_MOV_B32_]]
    ; WAVE64: [[COPY2:%[0-9]+]]:sreg_64_xexec = COPY [[S_OR_B32_]]
    ; WAVE64: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY2]]
    ; WAVE64: S_ENDPGM 0, implicit [[COPY3]]
    ; WAVE32-LABEL: name: copy_select_constrain_vcc_result_reg_wave32
    ; WAVE32: liveins: $vgpr0
    ; WAVE32: $vcc_hi = IMPLICIT_DEF
    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE32: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1
    ; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
    ; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[S_MOV_B32_]], implicit $exec
    ; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]
    ; WAVE32: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[S_OR_B32_]]
    ; WAVE32: S_ENDPGM 0, implicit [[COPY1]]
    %1:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s1) = G_TRUNC %1(s32)
    %2:sgpr(s1) = G_CONSTANT i1 true
    %6:sgpr(s32) = G_CONSTANT i32 0
    %7:sgpr(p1) = G_IMPLICIT_DEF
    %9:vcc(s1) = COPY %0(s1)
    %10:vcc(s1) = COPY %2(s1)
    %8:vcc(s1) = G_OR %9, %10
    %3:sreg_32_xm0(s1) = COPY %8(s1)
    S_ENDPGM 0, implicit %3

...

# Works for wave64, should fail for wave32
---
name:            copy_select_constrain_vcc_result_reg_wave64
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0

    ; WAVE64-LABEL: name: copy_select_constrain_vcc_result_reg_wave64
    ; WAVE64: liveins: $vgpr0
    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE64: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1
    ; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
    ; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[S_MOV_B32_]], implicit $exec
    ; WAVE64: [[S_OR_B64_:%[0-9]+]]:sreg_64 = S_OR_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]
    ; WAVE64: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY [[S_OR_B64_]]
    ; WAVE64: S_ENDPGM 0, implicit [[COPY1]]
    ; WAVE32-LABEL: name: copy_select_constrain_vcc_result_reg_wave64
    ; WAVE32: liveins: $vgpr0
    ; WAVE32: $vcc_hi = IMPLICIT_DEF
    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE32: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1
    ; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
    ; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[S_MOV_B32_]], implicit $exec
    ; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_OR_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]
    ; WAVE32: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY [[S_OR_B32_]]
    ; WAVE32: S_ENDPGM 0, implicit [[COPY1]]
    %1:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s1) = G_TRUNC %1(s32)
    %2:sgpr(s1) = G_CONSTANT i1 true
    %6:sgpr(s32) = G_CONSTANT i32 0
    %7:sgpr(p1) = G_IMPLICIT_DEF
    %9:vcc(s1) = COPY %0(s1)
    %10:vcc(s1) = COPY %2(s1)
    %8:vcc(s1) = G_OR %9, %10
    %3:sreg_64_xexec(s1) = COPY %8(s1)
    S_ENDPGM 0, implicit %3

...