test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.mbcnt.lo.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o -  | FileCheck -check-prefix=GCN %s

# FIXME: Need to deal with constant bus restriction
# ---
# name: mbcnt_lo_ss
# legalized: true
# regBankSelected: true

# body: |
#   bb.0:
#     liveins: $sgpr0, $sgpr1
#     %0:sgpr(s32) = COPY $sgpr0
#     %1:sgpr(s32) = COPY $sgpr1
#     %2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.mbcnt.lo), %0, %1
#     S_ENDPGM 0, implicit %2
# ...

---
name: mbcnt_lo_sv
legalized: true
regBankSelected: true

body: |
  bb.0:
    liveins: $sgpr0, $vgpr0
    ; GCN-LABEL: name: mbcnt_lo_sv
    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN: [[V_MBCNT_LO_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_MBCNT_LO_U32_B32_e64 [[COPY]], [[COPY1]], implicit $exec
    ; GCN: S_ENDPGM 0, implicit [[V_MBCNT_LO_U32_B32_e64_]]
    %0:sgpr(s32) = COPY $sgpr0
    %1:vgpr(s32) = COPY $vgpr0
    %2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.mbcnt.lo), %0, %1
    S_ENDPGM 0, implicit %2
...

---
name: smin_s32_vs
legalized: true
regBankSelected: true

body: |
  bb.0:
    liveins: $sgpr0, $vgpr0
    ; GCN-LABEL: name: smin_s32_vs
    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GCN: [[V_MBCNT_LO_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_MBCNT_LO_U32_B32_e64 [[COPY]], [[COPY1]], implicit $exec
    ; GCN: S_ENDPGM 0, implicit [[V_MBCNT_LO_U32_B32_e64_]]
    %0:vgpr(s32) = COPY $vgpr0
    %1:sgpr(s32) = COPY $sgpr0
    %2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.mbcnt.lo), %0, %1
    S_ENDPGM 0, implicit %2
...

---
name: smin_s32_vv
legalized: true
regBankSelected: true

body: |
  bb.0:
    liveins: $vgpr0, $vgpr1
    ; GCN-LABEL: name: smin_s32_vv
    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GCN: [[V_MBCNT_LO_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_MBCNT_LO_U32_B32_e64 [[COPY]], [[COPY1]], implicit $exec
    ; GCN: S_ENDPGM 0, implicit [[V_MBCNT_LO_U32_B32_e64_]]
    %0:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr1
    %2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.mbcnt.lo), %0, %1
    S_ENDPGM 0, implicit %2
...