test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmed3.s16.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs %s -o -  | FileCheck -check-prefix=GCN %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=2 -pass-remarks-missed='gisel*'  %s -o /dev/null 2>&1 | FileCheck -check-prefix=VI-ERR %s

# VI-ERR-NOT: remark
# VI-ERR: remark: <unknown>:0:0: cannot select: %6:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %3:vgpr(s16), %4:vgpr(s16), %5:vgpr(s16) (in function: fmed3_s16_vvvv)
# VI-ERR-NEXT: remark: <unknown>:0:0: cannot select: %6:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %3:sgpr(s16), %4:vgpr(s16), %5:vgpr(s16) (in function: fmed3_s16_vsvv)
# VI-ERR-NOT: remark
---
name: fmed3_s16_vvvv
legalized: true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins: $vgpr0, $vgpr1, $vgpr2

    ; GCN-LABEL: name: fmed3_s16_vvvv
    ; GCN: liveins: $vgpr0, $vgpr1, $vgpr2
    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
    ; GCN: [[V_MED3_F16_:%[0-9]+]]:vgpr_32 = V_MED3_F16 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
    ; GCN: S_ENDPGM 0, implicit [[V_MED3_F16_]]
    %0:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr1
    %2:vgpr(s32) = COPY $vgpr2
    %3:vgpr(s16) = G_TRUNC %0
    %4:vgpr(s16) = G_TRUNC %1
    %5:vgpr(s16) = G_TRUNC %2
    %6:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %3, %4, %5
    S_ENDPGM 0, implicit %6
...

---
name: fmed3_s16_vsvv
legalized: true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins: $sgpr0, $vgpr0, $vgpr1

    ; GCN-LABEL: name: fmed3_s16_vsvv
    ; GCN: liveins: $sgpr0, $vgpr0, $vgpr1
    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GCN: [[V_MED3_F16_:%[0-9]+]]:vgpr_32 = V_MED3_F16 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
    ; GCN: S_ENDPGM 0, implicit [[V_MED3_F16_]]
    %0:sgpr(s32) = COPY $sgpr0
    %1:vgpr(s32) = COPY $vgpr0
    %2:vgpr(s32) = COPY $vgpr1
    %3:sgpr(s16) = G_TRUNC %0
    %4:vgpr(s16) = G_TRUNC %1
    %5:vgpr(s16) = G_TRUNC %2
    %6:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %3, %4, %5
    S_ENDPGM 0, implicit %6
...