| commit | 7684aab92af11ee8bc1a3239ac6bde5c0c110ef6 | [log] [tgz] |
|---|---|---|
| author | Tim Renouf <tpr.llvm@botech.co.uk> | Fri Mar 22 10:11:21 2019 +0000 |
| committer | Tim Renouf <tpr.llvm@botech.co.uk> | Fri Mar 22 10:11:21 2019 +0000 |
| tree | 39046b821b16b6c5d8ed8ff0e7ae1961a00f3499 | |
| parent | aa5b4e00ae035b5e4ef55a295b5760e04a71fc16 [diff] |
[AMDGPU] Added v5i32 and v5f32 register classes They are not used by anything yet, but a subsequent commit will start using them for image ops that return 5 dwords. Differential Revision: https://reviews.llvm.org/D58903 Change-Id: I63e1904081e39a6d66e4eb96d51df25ad399d271 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356735 91177308-0d34-0410-b5e6-96231b3b80d8