[SelectionDAGBuilder] Refactor visitInlineAsm. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350837 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 9350084..7e1e63c 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -7476,21 +7476,6 @@
return CurOp;
}
-/// Fill \p Regs with \p NumRegs new virtual registers of type \p RegVT
-/// \return true if it has succeeded, false otherwise
-static bool createVirtualRegs(SmallVector<unsigned, 4> &Regs, unsigned NumRegs,
- MVT RegVT, SelectionDAG &DAG) {
- const TargetLowering &TLI = DAG.getTargetLoweringInfo();
- MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
- for (unsigned i = 0, e = NumRegs; i != e; ++i) {
- if (const TargetRegisterClass *RC = TLI.getRegClassFor(RegVT))
- Regs.push_back(RegInfo.createVirtualRegister(RC));
- else
- return false;
- }
- return true;
-}
-
namespace {
class ExtraFlags {
@@ -7547,12 +7532,10 @@
unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
unsigned ResNo = 0; // ResNo - The result number of the next output.
- for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
- ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
+ for (auto &T : TargetConstraints) {
+ ConstraintOperands.push_back(SDISelAsmOperandInfo(T));
SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
- MVT OpVT = MVT::Other;
-
// Compute the value type for each operand.
if (OpInfo.Type == InlineAsm::isInput ||
(OpInfo.Type == InlineAsm::isOutput && OpInfo.isIndirect)) {
@@ -7566,39 +7549,37 @@
OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
}
- OpVT =
+ OpInfo.ConstraintVT =
OpInfo
.getCallOperandValEVT(*DAG.getContext(), TLI, DAG.getDataLayout())
.getSimpleVT();
- }
-
- if (OpInfo.Type == InlineAsm::isOutput && !OpInfo.isIndirect) {
+ } else if (OpInfo.Type == InlineAsm::isOutput && !OpInfo.isIndirect) {
// The return value of the call is this value. As such, there is no
// corresponding argument.
assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
- OpVT = TLI.getSimpleValueType(DAG.getDataLayout(),
- STy->getElementType(ResNo));
+ OpInfo.ConstraintVT = TLI.getSimpleValueType(
+ DAG.getDataLayout(), STy->getElementType(ResNo));
} else {
assert(ResNo == 0 && "Asm only has one result!");
- OpVT = TLI.getSimpleValueType(DAG.getDataLayout(), CS.getType());
+ OpInfo.ConstraintVT =
+ TLI.getSimpleValueType(DAG.getDataLayout(), CS.getType());
}
++ResNo;
+ } else {
+ OpInfo.ConstraintVT = MVT::Other;
}
- OpInfo.ConstraintVT = OpVT;
-
if (!hasMemory)
hasMemory = OpInfo.hasMemory(TLI);
// Determine if this InlineAsm MayLoad or MayStore based on the constraints.
- // FIXME: Could we compute this on OpInfo rather than TargetConstraints[i]?
- auto TargetConstraint = TargetConstraints[i];
+ // FIXME: Could we compute this on OpInfo rather than T?
// Compute the constraint code and ConstraintType to use.
- TLI.ComputeConstraintToUse(TargetConstraint, SDValue());
+ TLI.ComputeConstraintToUse(T, SDValue());
- ExtraInfo.update(TargetConstraint);
+ ExtraInfo.update(T);
}
SDValue Chain, Flag;
@@ -7612,9 +7593,7 @@
// Second pass over the constraints: compute which constraint option to use
// and assign registers to constraints that want a specific physreg.
- for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
- SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
-
+ for (SDISelAsmOperandInfo &OpInfo : ConstraintOperands) {
// If this is an output operand with a matching input operand, look up the
// matching input. If their types mismatch, e.g. one is an integer, the
// other is floating point, or their sizes are different, flag it as an
@@ -7654,19 +7633,18 @@
SDISelAsmOperandInfo &RefOpInfo =
OpInfo.isMatchingInputConstraint()
? ConstraintOperands[OpInfo.getMatchedOperand()]
- : ConstraintOperands[i];
+ : OpInfo;
if (RefOpInfo.ConstraintType == TargetLowering::C_Register)
GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo, RefOpInfo);
}
// Third pass - Loop over all of the operands, assigning virtual or physregs
// to register class operands.
- for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
- SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
+ for (SDISelAsmOperandInfo &OpInfo : ConstraintOperands) {
SDISelAsmOperandInfo &RefOpInfo =
OpInfo.isMatchingInputConstraint()
? ConstraintOperands[OpInfo.getMatchedOperand()]
- : ConstraintOperands[i];
+ : OpInfo;
// C_Register operands have already been allocated, Other/Memory don't need
// to be.
@@ -7698,9 +7676,7 @@
// IndirectStoresToEmit - The set of stores to emit after the inline asm node.
std::vector<std::pair<RegsForValue, Value *>> IndirectStoresToEmit;
- for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
- SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
-
+ for (SDISelAsmOperandInfo &OpInfo : ConstraintOperands) {
switch (OpInfo.Type) {
case InlineAsm::isOutput:
if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
@@ -7778,9 +7754,12 @@
MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
SmallVector<unsigned, 4> Regs;
- if (!createVirtualRegs(Regs,
- InlineAsm::getNumOperandRegisters(OpFlag),
- RegVT, DAG)) {
+ if (const TargetRegisterClass *RC = TLI.getRegClassFor(RegVT)) {
+ unsigned NumRegs = InlineAsm::getNumOperandRegisters(OpFlag);
+ MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
+ for (unsigned i = 0; i != NumRegs; ++i)
+ Regs.push_back(RegInfo.createVirtualRegister(RC));
+ } else {
emitInlineAsmError(CS, "inline asm error: This value type register "
"class is not natively supported!");
return;
