5cbc524c2581f2494c8ec486a5a28949d71979ee - llvm

commit	5cbc524c2581f2494c8ec486a5a28949d71979ee	[log] [tgz]
author	Craig Topper <craig.topper@intel.com>	Sat Feb 02 06:21:54 2019 +0000
committer	Craig Topper <craig.topper@intel.com>	Sat Feb 02 06:21:54 2019 +0000
tree	15d9db6a9e35bc1d54a8cafd5328b7c68ebd4a21
parent	7ab3c4f08545bea0705e1ea016743cea3e54f9b1 [diff]

[X86][SSE]: Adding full coverage of MC encoding tests for the SSE isa sets.<NFC>

Summary:
NFC.
Adding MC regressions tests to cover all the SSE ISA sets as follows:
SSE, SSE2, SSE3, SSE4, SSE42, SSEMXCSR, SSE_PREFETCH, SSSE3

This patch is part of a larger task to cover MC encoding of all X86 ISA Sets.
See revision: https://reviews.llvm.org/D39952

Patch by Gadi Haber and Wang Tianqing

Reviewers: RKSimon, zvi, craig.topper, AndreiGrischenko, gadi.haber, LuoYuanke

Reviewed By: craig.topper

Subscribers: jfb, llvm-commits

Differential Revision: https://reviews.llvm.org/D40387

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352955 91177308-0d34-0410-b5e6-96231b3b80d8

test/MC/X86/MMX-32.s[diff]
test/MC/X86/MMX-64.s[diff]
test/MC/X86/SSE-32.s[Added - diff]
test/MC/X86/SSE-64.s[Added - diff]
test/MC/X86/SSE2-32.s[Added - diff]
test/MC/X86/SSE2-64.s[Added - diff]
test/MC/X86/SSE3-32.s[Added - diff]
test/MC/X86/SSE3-64.s[Added - diff]
test/MC/X86/SSE41-32.s[Added - diff]
test/MC/X86/SSE41-64.s[Added - diff]
test/MC/X86/SSE42-32.s[Added - diff]
test/MC/X86/SSE42-64.s[Added - diff]
test/MC/X86/SSE4a-32.s[Added - diff]
test/MC/X86/SSE4a-64.s[Added - diff]
test/MC/X86/SSEMXCSR-32.s[Added - diff]
test/MC/X86/SSEMXCSR-64.s[Added - diff]
test/MC/X86/SSE_PREFETCH-32.s[Added - diff]
test/MC/X86/SSE_PREFETCH-64.s[Added - diff]
test/MC/X86/SSSE3-32.s[Added - diff]
test/MC/X86/SSSE3-64.s[Added - diff]

20 files changed

tree: 15d9db6a9e35bc1d54a8cafd5328b7c68ebd4a21