blob: cd72edd729ae7251bb044bc4eccd337977215146 [file] [log] [blame]
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL
--- |
define double @test(float %a) {
entry:
%conv = fpext float %a to double
ret double %conv
}
...
---
name: test
alignment: 4
legalized: true
regBankSelected: true
registers:
- { id: 0, class: vecr, preferred-register: '' }
- { id: 1, class: vecr, preferred-register: '' }
- { id: 2, class: vecr, preferred-register: '' }
- { id: 3, class: vecr, preferred-register: '' }
liveins:
fixedStack:
stack:
constants:
body: |
bb.1.entry:
liveins: $xmm0
; ALL-LABEL: name: test
; ALL: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
; ALL: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
; ALL: [[CVTSS2SDrr:%[0-9]+]]:fr64 = CVTSS2SDrr [[COPY1]]
; ALL: [[COPY2:%[0-9]+]]:vr128 = COPY [[CVTSS2SDrr]]
; ALL: $xmm0 = COPY [[COPY2]]
; ALL: RET 0, implicit $xmm0
%1:vecr(s128) = COPY $xmm0
%0:vecr(s32) = G_TRUNC %1(s128)
%2:vecr(s64) = G_FPEXT %0(s32)
%3:vecr(s128) = G_ANYEXT %2(s64)
$xmm0 = COPY %3(s128)
RET 0, implicit $xmm0
...