# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

---
name: insert_vector_elt_v4i32_s_s_k
legalized: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr5
    ; CHECK-LABEL: name: insert_vector_elt_v4i32_s_s_k
    ; CHECK: [[COPY:%[0-9]+]]:sgpr(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
    ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
    ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
    ; CHECK: [[IVEC:%[0-9]+]]:sgpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[COPY1]](s32), [[C]](s32)
    ; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[IVEC]](<4 x s32>)
    %0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
    %1:_(s32) = COPY $sgpr5
    %2:_(s32) = G_CONSTANT i32 0
    %3:_(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
    $sgpr0_sgpr1_sgpr2_sgpr3 = COPY %3
...

---
name: insert_vector_elt_v4i32_v_s_k
legalized: true

body: |
  bb.0:
    liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr5
    ; CHECK-LABEL: name: insert_vector_elt_v4i32_v_s_k
    ; CHECK: [[COPY:%[0-9]+]]:vgpr(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
    ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
    ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
    ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
    ; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
    ; CHECK: [[IVEC:%[0-9]+]]:vgpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[COPY2]](s32), [[COPY3]](s32)
    ; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[IVEC]](<4 x s32>)
    %0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
    %1:_(s32) = COPY $sgpr5
    %2:_(s32) = G_CONSTANT i32 0
    %3:_(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
    $sgpr0_sgpr1_sgpr2_sgpr3 = COPY %3
...

---
name: insert_vector_elt_v4i32_s_v_k
legalized: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $vgpr5
    ; CHECK-LABEL: name: insert_vector_elt_v4i32_s_v_k
    ; CHECK: [[COPY:%[0-9]+]]:sgpr(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
    ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
    ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
    ; CHECK: [[COPY2:%[0-9]+]]:vgpr(<4 x s32>) = COPY [[COPY]](<4 x s32>)
    ; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
    ; CHECK: [[IVEC:%[0-9]+]]:vgpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY2]], [[COPY1]](s32), [[COPY3]](s32)
    ; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[IVEC]](<4 x s32>)
    %0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
    %1:_(s32) = COPY $vgpr2
    %2:_(s32) = G_CONSTANT i32 0
    %3:_(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
    $sgpr0_sgpr1_sgpr2_sgpr3 = COPY %3
...

---
name: insert_vector_elt_var_v4i32_s_s_s
legalized: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr5, $sgpr6
    ; CHECK-LABEL: name: insert_vector_elt_var_v4i32_s_s_s
    ; CHECK: [[COPY:%[0-9]+]]:sgpr(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
    ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
    ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr6
    ; CHECK: [[COPY3:%[0-9]+]]:vgpr(<4 x s32>) = COPY [[COPY]](<4 x s32>)
    ; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
    ; CHECK: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32)
    ; CHECK: [[IVEC:%[0-9]+]]:vgpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY3]], [[COPY4]](s32), [[COPY5]](s32)
    ; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[IVEC]](<4 x s32>)
    %0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
    %1:_(s32) = COPY $sgpr5
    %2:_(s32) = COPY $sgpr6
    %3:_(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
    $sgpr0_sgpr1_sgpr2_sgpr3 = COPY %3
...

---
name: insert_vector_elt_var_v4i32_s_s_v
legalized: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr5, $vgpr6
    ; CHECK-LABEL: name: insert_vector_elt_var_v4i32_s_s_v
    ; CHECK: [[COPY:%[0-9]+]]:sgpr(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
    ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
    ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr6
    ; CHECK: [[COPY3:%[0-9]+]]:vgpr(<4 x s32>) = COPY [[COPY]](<4 x s32>)
    ; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
    ; CHECK: [[IVEC:%[0-9]+]]:vgpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY3]], [[COPY4]](s32), [[COPY2]](s32)
    ; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[IVEC]](<4 x s32>)
    %0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
    %1:_(s32) = COPY $sgpr5
    %2:_(s32) = COPY $vgpr6
    %3:_(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
    $sgpr0_sgpr1_sgpr2_sgpr3 = COPY %3
...

---
name: insert_vector_elt_var_v4i32_v_s_v
legalized: true

body: |
  bb.0:
    liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr5, $vgpr6
    ; CHECK-LABEL: name: insert_vector_elt_var_v4i32_v_s_v
    ; CHECK: [[COPY:%[0-9]+]]:vgpr(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
    ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
    ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr6
    ; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
    ; CHECK: [[IVEC:%[0-9]+]]:vgpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[COPY3]](s32), [[COPY2]](s32)
    ; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[IVEC]](<4 x s32>)
    %0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
    %1:_(s32) = COPY $sgpr5
    %2:_(s32) = COPY $vgpr6
    %3:_(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
    $sgpr0_sgpr1_sgpr2_sgpr3 = COPY %3
...

---
name: insert_vector_elt_var_v4i32_v_v_v
legalized: true

body: |
  bb.0:
    liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr5, $vgpr6
    ; CHECK-LABEL: name: insert_vector_elt_var_v4i32_v_v_v
    ; CHECK: [[COPY:%[0-9]+]]:vgpr(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
    ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr5
    ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr6
    ; CHECK: [[IVEC:%[0-9]+]]:vgpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[COPY1]](s32), [[COPY2]](s32)
    ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[IVEC]](<4 x s32>)
    %0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
    %1:_(s32) = COPY $vgpr5
    %2:_(s32) = COPY $vgpr6
    %3:_(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
    $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %3
...