test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract-vector-elt.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

---
name: extract_vector_elt_0_v2i32_s
legalized: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1
    ; CHECK-LABEL: name: extract_vector_elt_0_v2i32_s
    ; CHECK: [[COPY:%[0-9]+]]:sgpr(<2 x s32>) = COPY $sgpr0_sgpr1
    ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
    ; CHECK: [[EVEC:%[0-9]+]]:sgpr(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x s32>), [[C]](s32)
    ; CHECK: $vgpr0 = COPY [[EVEC]](s32)
    %0:_(<2 x s32>) = COPY $sgpr0_sgpr1
    %1:_(s32) = G_CONSTANT i32 0
    %2:_(s32) = G_EXTRACT_VECTOR_ELT %0, %1
    $vgpr0 = COPY %2
...


---
name: extract_vector_elt_0_v4i32_s
legalized: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1_sgpr2_sgpr3
    ; CHECK-LABEL: name: extract_vector_elt_0_v4i32_s
    ; CHECK: [[COPY:%[0-9]+]]:sgpr(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
    ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
    ; CHECK: [[EVEC:%[0-9]+]]:sgpr(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<4 x s32>), [[C]](s32)
    ; CHECK: $vgpr0 = COPY [[EVEC]](s32)
    %0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
    %1:_(s32) = G_CONSTANT i32 0
    %2:_(s32) = G_EXTRACT_VECTOR_ELT %0, %1
    $vgpr0 = COPY %2
...