# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck %s

---
name: test_zext_s32_to_s64
body: |
  bb.0.entry:
    liveins: $vgpr0

    ; CHECK-LABEL: name: test_zext_s32_to_s64
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
    ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s32)
    ; CHECK: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
    %0:_(s32) = COPY $vgpr0
    %1:_(s64) = G_ZEXT %0
    $vgpr0_vgpr1 = COPY %1
...

---
name: test_zext_s16_to_s64
body: |
  bb.0.entry:
    liveins: $vgpr0

    ; CHECK-LABEL: name: test_zext_s16_to_s64
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
    ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s32)
    ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C]]
    ; CHECK: $vgpr0_vgpr1 = COPY [[AND]](s64)
    %0:_(s32) = COPY $vgpr0
    %1:_(s16) = G_TRUNC %0
    %2:_(s64) = G_ZEXT %1
    $vgpr0_vgpr1 = COPY %2
...

---
name: test_zext_s16_to_s32
body: |
  bb.0.entry:
    liveins: $vgpr0

    ; CHECK-LABEL: name: test_zext_s16_to_s32
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
    ; CHECK: $vgpr0 = COPY [[AND]](s32)
    %0:_(s32) = COPY $vgpr0
    %1:_(s16) = G_TRUNC %0
    %2:_(s32) = G_ZEXT %1
    $vgpr0 = COPY %2
...

---
name: test_zext_i1_to_s32
body: |
  bb.0.entry:
    liveins: $vgpr0

    ; CHECK-LABEL: name: test_zext_i1_to_s32
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
    ; CHECK: $vgpr0 = COPY [[AND]](s32)
    %0:_(s32) = COPY $vgpr0
    %1:_(s1) = G_TRUNC %0
    %2:_(s32) = G_ZEXT %1
    $vgpr0 = COPY %2
...