test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-xchg-flat.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=bonaire -O0 -run-pass=legalizer -o - %s | FileCheck %s
# RUN: not llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=legalizer -o /dev/null %s 2>&1 | FileCheck -check-prefix=ERROR %s

# ERROR: LLVM ERROR: unable to legalize instruction: %2:_(s32) = G_ATOMICRMW_XCHG %0:_(p0), %1:_ :: (load store seq_cst 4) (in function: atomicrmw_xchg_flat_i32)


---
name: atomicrmw_xchg_flat_i32

body: |
  bb.0:
    liveins: $sgpr0_sgpr1, $sgpr2
    ; CHECK-LABEL: name: atomicrmw_xchg_flat_i32
    ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $sgpr0_sgpr1
    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr2
    ; CHECK: [[ATOMICRMW_XCHG:%[0-9]+]]:_(s32) = G_ATOMICRMW_XCHG [[COPY]](p0), [[COPY1]] :: (load store seq_cst 4)
    %0:_(p0) = COPY $sgpr0_sgpr1
    %1:_(s32) = COPY $sgpr2
    %2:_(s32) = G_ATOMICRMW_XCHG %0, %1 :: (load store seq_cst 4, addrspace 0)
...

---
name: atomicrmw_xchg_flat_i64

body: |
  bb.0:
    liveins: $sgpr0_sgpr1, $sgpr2
    ; CHECK-LABEL: name: atomicrmw_xchg_flat_i64
    ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $sgpr0_sgpr1
    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr2
    ; CHECK: [[ATOMICRMW_XCHG:%[0-9]+]]:_(s32) = G_ATOMICRMW_XCHG [[COPY]](p0), [[COPY1]] :: (load store seq_cst 4)
    %0:_(p0) = COPY $sgpr0_sgpr1
    %1:_(s32) = COPY $sgpr2
    %2:_(s32) = G_ATOMICRMW_XCHG %0, %1 :: (load store seq_cst 4, addrspace 0)
...