tree 2f33034a771adefbf72ed5c83775e64a9fe0732b
parent f4baea281dceff411d61ef109ac2072566459196
author Simon Pilgrim <llvm-dev@redking.me.uk> 1553454395 +0000
committer Simon Pilgrim <llvm-dev@redking.me.uk> 1553454395 +0000

[X86][SSE41] Start shuffle combining from ZERO_EXTEND_VECTOR_INREG (PR40685)

Enable SSE41 ZERO_EXTEND_VECTOR_INREG shuffle combines - for the PMOVZX(PSHUFD(V)) -> UNPCKH(V,0) pattern we reduce the shuffles (port5-bottleneck on Intel) at the expense of creating a zero (pxor v,v) and an extra register move - which is a good trade off as these are pretty cheap and in most cases it doesn't increase register pressure.

This also exposed a missed opportunity to use combine to ZERO_EXTEND_VECTOR_INREG with folded loads - even if we're in the float domain.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356864 91177308-0d34-0410-b5e6-96231b3b80d8