# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=i386-linux-gnu   -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X32
# RUN: llc -O0 -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X64
--- |
  define void @trunc_check() {
    ret void
  }

...
---
name:            trunc_check
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
body:             |
  bb.1 (%ir-block.0):
    ; X32-LABEL: name: trunc_check
    ; X32: [[DEF:%[0-9]+]]:_(s32) = IMPLICIT_DEF
    ; X32: [[DEF1:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
    ; X32: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
    ; X32: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[DEF]](s32)
    ; X32: [[AND:%[0-9]+]]:_(s8) = G_AND [[TRUNC]], [[C]]
    ; X32: G_STORE [[AND]](s8), [[DEF1]](p0) :: (store 1)
    ; X32: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[DEF]](s32)
    ; X32: G_STORE [[TRUNC1]](s8), [[DEF1]](p0) :: (store 1)
    ; X32: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[DEF]](s32)
    ; X32: G_STORE [[TRUNC2]](s16), [[DEF1]](p0) :: (store 2)
    ; X32: RET 0
    ; X64-LABEL: name: trunc_check
    ; X64: [[DEF:%[0-9]+]]:_(s32) = IMPLICIT_DEF
    ; X64: [[DEF1:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
    ; X64: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
    ; X64: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[DEF]](s32)
    ; X64: [[AND:%[0-9]+]]:_(s8) = G_AND [[TRUNC]], [[C]]
    ; X64: G_STORE [[AND]](s8), [[DEF1]](p0) :: (store 1)
    ; X64: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[DEF]](s32)
    ; X64: G_STORE [[TRUNC1]](s8), [[DEF1]](p0) :: (store 1)
    ; X64: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[DEF]](s32)
    ; X64: G_STORE [[TRUNC2]](s16), [[DEF1]](p0) :: (store 2)
    ; X64: RET 0
    %0(s32) = IMPLICIT_DEF
    %1(s1)  = G_TRUNC %0(s32)
    %4:_(p0) = G_IMPLICIT_DEF
    G_STORE %1, %4 :: (store 1)

    %2(s8)  = G_TRUNC %0(s32)
    G_STORE %2, %4 :: (store 1)

    %3(s16) = G_TRUNC %0(s32)
    G_STORE %3, %4 :: (store 2)
    RET 0

...