tree 7d147558b306c9bfac32e9bfd7edcc572f832db3
parent 8bb1682aae0ea8b84374698df68b62435fcec10e
author Lei Liu <lei.liu2@windriver.com> 1474443701 +0000
committer Lei Liu <lei.liu2@windriver.com> 1474443701 +0000

AArch64: Set shift bit of TLSLE HI12 add instruction

Summary: AArch64 LLVM assembler emits add instruction without shift bit to calculate the higher 12-bit address of TLS variables in local exec model.  This generates wrong code sequence to access TLS variables with thread offset larger than 0x1000.

Reviewers: t.p.northover, peter.smith, rovka

Subscribers: salim.nasser, aemerson, llvm-commits, rengolin

Differential Revision: https://reviews.llvm.org/D24702

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@282057 91177308-0d34-0410-b5e6-96231b3b80d8