| commit | 2fdd5d38064dc6aaf18179597fff0bde403a948d | [log] [tgz] |
|---|---|---|
| author | Alex Bradbury <asb@lowrisc.org> | Wed Sep 19 10:54:22 2018 +0000 |
| committer | Alex Bradbury <asb@lowrisc.org> | Wed Sep 19 10:54:22 2018 +0000 |
| tree | cc5c0683ff3a6b569e6d4d2ce5115062641bb8dd | |
| parent | c75b449af658351186d2832909a8a28800600312 [diff] |
[RISCV] Codegen for i8, i16, and i32 atomicrmw with RV32A Introduce a new RISCVExpandPseudoInsts pass to expand atomic pseudo-instructions after register allocation. This is necessary in order to ensure that register spills aren't introduced between LL and SC, thus breaking the forward progress guarantee for the operation. AArch64 does something similar for CmpXchg (though only at O0), and Mips is moving towards this approach (see D31287). See also [this mailing list post](http://lists.llvm.org/pipermail/llvm-dev/2016-May/099490.html) from James Knight, which summarises the issues with lowering to ll/sc in IR or pre-RA. See the [accompanying RFC thread](http://lists.llvm.org/pipermail/llvm-dev/2018-June/123993.html) for an overview of the lowering strategy. Differential Revision: https://reviews.llvm.org/D47882 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342534 91177308-0d34-0410-b5e6-96231b3b80d8