test/CodeGen/X86/GlobalISel/legalize-memop-scalar.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X64
# RUN: llc -mtriple=i386-linux-gnu   -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X32

--- |
  define void @test_memop_s8tos32() {
    ret void
  }

  define void @test_memop_s64() {
    ret void
  }
...
---
name:            test_memop_s8tos32
alignment:       4
legalized:       false
regBankSelected: false
registers:
  - { id: 0, class: _, preferred-register: '' }
  - { id: 1, class: _, preferred-register: '' }
  - { id: 2, class: _, preferred-register: '' }
  - { id: 3, class: _, preferred-register: '' }
  - { id: 4, class: _, preferred-register: '' }
  - { id: 5, class: _, preferred-register: '' }
  - { id: 6, class: _, preferred-register: '' }
  - { id: 7, class: _, preferred-register: '' }
  - { id: 8, class: _, preferred-register: '' }
  - { id: 9, class: _, preferred-register: '' }
  - { id: 10, class: _, preferred-register: '' }
body:             |
  bb.1 (%ir-block.0):
    liveins: $rdi

    ; X64-LABEL: name: test_memop_s8tos32
    ; X64: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
    ; X64: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[DEF]](p0) :: (load 1)
    ; X64: [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[DEF]](p0) :: (load 1)
    ; X64: [[LOAD2:%[0-9]+]]:_(s16) = G_LOAD [[DEF]](p0) :: (load 2)
    ; X64: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p0) :: (load 4)
    ; X64: [[LOAD4:%[0-9]+]]:_(p0) = G_LOAD [[DEF]](p0) :: (load 8)
    ; X64: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
    ; X64: [[COPY:%[0-9]+]]:_(s8) = COPY [[LOAD]](s8)
    ; X64: [[AND:%[0-9]+]]:_(s8) = G_AND [[COPY]], [[C]]
    ; X64: G_STORE [[AND]](s8), [[DEF]](p0) :: (store 1)
    ; X64: G_STORE [[LOAD1]](s8), [[DEF]](p0) :: (store 1)
    ; X64: G_STORE [[LOAD2]](s16), [[DEF]](p0) :: (store 2)
    ; X64: G_STORE [[LOAD3]](s32), [[DEF]](p0) :: (store 4)
    ; X64: G_STORE [[LOAD4]](p0), [[DEF]](p0) :: (store 8)
    ; X32-LABEL: name: test_memop_s8tos32
    ; X32: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
    ; X32: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[DEF]](p0) :: (load 1)
    ; X32: [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[DEF]](p0) :: (load 1)
    ; X32: [[LOAD2:%[0-9]+]]:_(s16) = G_LOAD [[DEF]](p0) :: (load 2)
    ; X32: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p0) :: (load 4)
    ; X32: [[LOAD4:%[0-9]+]]:_(p0) = G_LOAD [[DEF]](p0) :: (load 8)
    ; X32: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
    ; X32: [[COPY:%[0-9]+]]:_(s8) = COPY [[LOAD]](s8)
    ; X32: [[AND:%[0-9]+]]:_(s8) = G_AND [[COPY]], [[C]]
    ; X32: G_STORE [[AND]](s8), [[DEF]](p0) :: (store 1)
    ; X32: G_STORE [[LOAD1]](s8), [[DEF]](p0) :: (store 1)
    ; X32: G_STORE [[LOAD2]](s16), [[DEF]](p0) :: (store 2)
    ; X32: G_STORE [[LOAD3]](s32), [[DEF]](p0) :: (store 4)
    ; X32: G_STORE [[LOAD4]](p0), [[DEF]](p0) :: (store 8)
    %0(p0) = IMPLICIT_DEF
    %9(s1) = G_LOAD %0(p0) :: (load 1)
    %1(s8) = G_LOAD %0(p0) :: (load 1)
    %2(s16) = G_LOAD %0(p0) :: (load 2)
    %3(s32) = G_LOAD %0(p0) :: (load 4)
    %4(p0) = G_LOAD %0(p0) :: (load 8)

    G_STORE %9, %0 :: (store 1)
    G_STORE %1, %0 :: (store 1)
    G_STORE %2, %0 :: (store 2)
    G_STORE %3, %0 :: (store 4)
    G_STORE %4, %0 :: (store 8)
...
---
name:            test_memop_s64
alignment:       4
legalized:       false
regBankSelected: false
registers:
  - { id: 0, class: _, preferred-register: '' }
  - { id: 1, class: _, preferred-register: '' }
  - { id: 2, class: _, preferred-register: '' }
liveins:
#
body:             |
  bb.1 (%ir-block.0):
    liveins: $rdi

    ; X64-LABEL: name: test_memop_s64
    ; X64: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
    ; X64: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[DEF]](p0) :: (load 8)
    ; X64: G_STORE [[LOAD]](s64), [[DEF]](p0) :: (store 8)
    ; X32-LABEL: name: test_memop_s64
    ; X32: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
    ; X32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p0) :: (load 4, align 8)
    ; X32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
    ; X32: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[DEF]], [[C]](s32)
    ; X32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[GEP]](p0) :: (load 4)
    ; X32: G_STORE [[LOAD]](s32), [[DEF]](p0) :: (store 4, align 8)
    ; X32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
    ; X32: [[GEP1:%[0-9]+]]:_(p0) = G_GEP [[DEF]], [[C1]](s32)
    ; X32: G_STORE [[LOAD1]](s32), [[GEP1]](p0) :: (store 4)
    %0(p0) = IMPLICIT_DEF
    %1(s64) = G_LOAD %0(p0) :: (load 8)

    G_STORE %1, %0 :: (store 8)

...